Alexander Edward

Publication Activity (10 Years)

Years Active: 2012-2018
Publications (10 Years): 9

Top Topics

Cmos Technology

Quantization Noise

Cmos Image Sensor

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Carlos Briseno-Vidrios, Dadian Zhou, Suraj Prakash, Qiyuan Liu, Alexander Edward, Eric G. Soenen, Martin Kinyua, José Silva-Martínez
A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs. IEEE J. Solid State Circuits 53 (11) (2018)
Qiyuan Liu, Alexander Edward, Dadian Zhou, José Silva-Martínez
A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26 (4) (2018)
Carlos Briseno-Vidrios, Dadian Zhou, Suraj Prakash, Qiyuan Liu, Alexander Edward, José Silva-Martínez
A 13bit 200MS/S pipeline ADC with current-mode MDACs. ISCAS (2017)
Carlos Briseno-Vidrios, Alexander Edward, Ayman Shafik, Samuel Palermo, José Silva-Martínez
A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage. IEEE J. Solid State Circuits 52 (3) (2017)
Qiyuan Liu, Alexander Edward, Martin Kinyua, Eric G. Soenen, José Silva-Martínez
A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques. IEEE J. Solid State Circuits 52 (6) (2017)
Qiyuan Liu, Alexander Edward, Carlos Briseno-Vidrios, Negar Rashidi, José Silva-Martínez
High-performance continuous-time MASH sigma-delta ADCs for broadband wireless applications. MWSCAS (2017)
Alexander Edward, Qiyuan Liu, Carlos Briseno-Vidrios, Martin Kinyua, Eric G. Soenen, Aydin Ilker Karsilayan, José Silva-Martínez
A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS. IEEE J. Solid State Circuits 52 (2) (2017)
Carlos Briseno-Vidrios, Alexander Edward, Negar Rashidi, José Silva-Martínez
A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer. IEEE J. Solid State Circuits 51 (6) (2016)
Carlos Briseno-Vidrios, Alexander Edward, Ayman Shafik, Samuel Palermo, José Silva-Martínez
A 75 MHz BW 68dB DR CT-ΣΔ modulator with single amplifier biquad filter and a broadband low-power common-gate summing technique. VLSIC (2015)
Alexander Edward, José Silva-Martínez
General Analysis of Feedback DAC's Clock Jitter in Continuous-Time Sigma-Delta Modulators. IEEE Trans. Circuits Syst. II Express Briefs (7) (2014)
Alexander Edward, Pak Kwong Chan
An Ultra-Low Voltage Analog Front End for Strain Gauge Sensory System Application in 0.18 µm CMOS. IEICE Trans. Electron. (4) (2012)