A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers.
Mohammad H. NaderiChulhyun ParkSuraj PrakashMartin KinyuaEric G. SoenenJosé Silva-MartínezPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2019)