A 1.5 ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links With Up to 40 Times Event-Rate Dependent Power Savings.
Carlos Zamarreño-RamosRaghavendra KulkarniJosé Silva-MartínezTeresa Serrano-GotarredonaBernabé Linares-BarrancoPublished in: IEEE Trans. Biomed. Circuits Syst. (2013)
Keyphrases
- energy dissipation
- random access memory
- low power
- high speed
- low voltage
- power system
- ibm power processor
- power losses
- power supply
- voltage sags
- shift register
- electrical power
- power grid
- low cost
- traffic flow
- wireless sensor networks
- single phase
- duty cycle
- reactive power
- chip design
- event detection
- power dissipation
- event driven
- power consumption
- power generation
- transmission line
- high density
- multithreading
- network simulator
- power allocation
- computational complexity
- analog to digital converter
- ad hoc networks
- processor core
- power quality
- power management