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A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS.

Haoyu QianQiyuan LiuJosé Silva-MartínezSebastian Hoyos
Published in: IEEE J. Solid State Circuits (2016)
Keyphrases
  • power consumption
  • power reduction
  • clock gating
  • low power
  • silicon on insulator
  • high speed
  • nm technology
  • cmos technology
  • power dissipation
  • power management
  • low cost
  • power saving
  • input data
  • database
  • single chip