A CMOS 1 Gb/s 5-Tap Fractionally-Spaced Equalizer.

David Hernandez-Garduno José Silva-Martínez

Published in: IEEE J. Solid State Circuits (2008)

Keyphrases

high speed
computer simulation
low power
decision feedback
low cost
analog vlsi
power consumption
power supply
circuit design
multipath
hidden markov models
vlsi circuits
neural network
image sequences
frame rate
learning algorithm
network size
focal plane
low voltage