José G. Delgado-Frias

ORCID

Publication Activity (10 Years)

Years Active: 1988-2022
Publications (10 Years): 14

Top Venues

MWSCAS

ISCAS

IEEE Trans. Circuits Syst. II Express Briefs

Ad Hoc Networks

Publications

Daniel Iparraguirre, José G. Delgado-Frias, Howard Heck
Asymmetric Crosstalk Harness Signaling for Common Eigenmode Elimination. IEEE Trans. Computers 71 (9) (2022)
Daniel Iparraguirre, José G. Delgado-Frias
Asymmetric Crosstalk Harnessed Signaling for Large 3D Routing Integration. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Daniel Iparraguirre, José G. Delgado-Frias
ACHS Optimizations on 3D Interconnect Arrangements. ISCAS (2022)
Daniel Iparraguirre, José G. Delgado-Frias, Howard Heck
A Crosstalk-Harnessed Signaling Enhancement that Eliminates Common-Mode Encoding. ISCAS (2021)
Michael A. Turi, José G. Delgado-Frias
Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating. IEEE Trans. Circuits Syst. II Express Briefs (4) (2020)
Rongyang Liu, José G. Delgado-Frias, Doug Boyce, Yi Qian, Rahul Khanna
Online Firmware Functional Validation Scheme Using Colored Petri Net Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (7) (2020)
José Silva-Martínez, José G. Delgado-Frias
MWSCAS Guest Editorial Special Issue Based on the 62nd International Midwest Symposium on Circuits and Systems. IEEE Trans. Circuits Syst. (10) (2020)
Michael A. Turi, José G. Delgado-Frias
and near-threshold performance of 8T FinFET SRAM cells. Integr. 57 (2017)
Rongyang Liu, José G. Delgado-Frias, Doug Boyce, Rahul Khanna
Firmware functional validation using a Colored Petri Net model. MWSCAS (2017)
Michael A. Turi, José G. Delgado-Frias
An implemented, initialization algorithm for many-dimension, Monte Carlo circuit simulations using Spice. CCWC (2017)
Johnathan Vee Cree, José G. Delgado-Frias
Autonomous management of a recursive area hierarchy for large scale wireless sensor networks using multiple parents. Ad Hoc Networks 39 (2016)
Rongyang Liu, José G. Delgado-Frias, Doug Boyce, Rahul Khanna
A real-time UEFI functional validation tool with behavior Colored Petri Net model. MWSCAS (2016)
José G. Delgado-Frias, Zhe Zhang, Michael A. Turi
Near-threshold CNTFET SRAM cell design with removed metallic CNT tolerance. ISCAS (2015)
Rongyang Liu, José G. Delgado-Frias, Doug Boyce, Rahul Khanna
UEFI USB bus initialization verification using Colored Petri Net. MWSCAS (2015)
Michael A. Turi, José G. Delgado-Frias
An evaluation of 6T and 8T FinFET SRAM cell leakage currents. MWSCAS (2014)
José Silva-Martínez, Edgar Sánchez-Sinencio, José G. Delgado-Frias, Randall L. Geiger
Welcome to MWSCAS 2014. MWSCAS (2014)
Zhe Zhang, José G. Delgado-Frias
Near-threshold CNTFET SRAM cell design with gated cell power supply. MWSCAS (2013)
Zhe Zhang, José G. Delgado-Frias
CNTFET 8T SRAM cell performance with near-threshold power supply scaling. ISCAS (2013)
Johnathan Vee Cree, José G. Delgado-Frias
Management of large-scale wireless sensor networks utilizing multi-parent recursive area hierarchies. IGCC (2013)
Johnathan Vee Cree, José G. Delgado-Frias, Mike Hughes, Brion Burghard, Kurt Silvers
NOA: A Scalable Multi-Parent Clustering Hierarchy for WSNs. ANT/MobiWIS (2012)
Jason Van Dyken, José G. Delgado-Frias
A superscalar processor for a medium-grain reconfigurable hardware. MWSCAS (2012)
Colby M. Gerik, Michael A. Turi, José G. Delgado-Frias
FinFET 3T and 3T1D dynamic RAM cells. MWSCAS (2012)
Zhe Zhang, José G. Delgado-Frias
CNTFET SRAM cell with tolerance to removed metallic CNTs. MWSCAS (2012)
Zhe Zhang, Michael A. Turi, José G. Delgado-Frias
SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cells. ACM Great Lakes Symposium on VLSI (2012)
José G. Delgado-Frias, Zhe Zhang, Michael A. Turi
Low power SRAM cell design for FinFET and CNTFET technologies. Green Computing Conference (2010)
Jason Van Dyken, José G. Delgado-Frias
FPGA schemes for minimizing the power-throughput trade-off in executing the Advanced Encryption Standard algorithm. J. Syst. Archit. 56 (2-3) (2010)
G. Ramirez-Conejo, Javier Díaz-Carmona, Agustín Ramírez-Agundis, A. Padilla-Medina, José G. Delgado-Frias
FPGA Implementation of Adjustable Wideband Fractional Delay FIR Filters. ReConFig (2010)
Ruirui Guo, José G. Delgado-Frias
IP Routing table compaction and sampling schemes to enhance TCAM cache performance. J. Syst. Archit. 55 (1) (2009)
Kylan Robinson, José G. Delgado-Frias
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures. ERSA (2009)
Michael A. Turi, José G. Delgado-Frias
Decreasing energy consumption in address decoders by means of selective precharge schemes. Microelectron. J. 40 (11) (2009)
Michael A. Turi, José G. Delgado-Frias
High-Performance Low-Power Selective Precharge Schemes for Address Decoders. IEEE Trans. Circuits Syst. II Express Briefs (9) (2008)
Michael A. Turi, José G. Delgado-Frias
High-performance low-power AND and Sense-Amp address decoders with selective precharging. ISCAS (2008)
Li Zhao, José G. Delgado-Frias, Krishnamoorthy Sivakumar
Performance analysis of multipath transmission over 802.11-based multihop ad hoc networks: a cross-layer perspective. IET Commun. 2 (2) (2008)
Mitchell J. Myjak, José G. Delgado-Frias
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance. IEEE Trans. Very Large Scale Integr. Syst. 16 (1) (2008)
Peter Sapaty, Masanori Sugisaka, José G. Delgado-Frias, Joaquim Filipe, Nikolay N. Mirenkov
Intelligent management of distributed dynamic sensor networks. Artif. Life Robotics 12 (1-2) (2008)
Jason Van Dyken, José G. Delgado-Frias, Sirisha Medidi
FPGA Schemes with Optimized Routing for the Advanced Encryption Standard. ERSA (2008)
Rongsen He, José G. Delgado-Frias
Fault Tolerant Interleaved Switching Fabrics For Scalable High-Performance Routers. IEEE Trans. Parallel Distributed Syst. 18 (12) (2007)
Li Zhao, José G. Delgado-Frias
MARS: Misbehavior Detection in Ad Hoc Networks. GLOBECOM (2007)
Rongsen He, José G. Delgado-Frias
Redundant Array of Independent Fabrics - An Architecture for Next Generation Network. GLOBECOM (2007)
H. Lui, José G. Delgado-Frias, Sirisha Medidi
Using a two-timer scheme to detect selfish nodes in mobile ad-hoc networks. Communications, Internet, and Information Technology (2007)
Mitchell J. Myjak, José G. Delgado-Frias
Medium-Grain Cells for Reconfigurable DSP Hardware. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2007)
Laurence Tianruo Yang, José G. Delgado-Frias, Yiming Li, Mohammed Y. Niamat, Dimitrios Soudris, Srinivasa Vemuru
Preface. Integr. 40 (2) (2007)
Hongxun Liu, José G. Delgado-Frias, Sirisha Medidi
Using a Cache Scheme to Detect Misbehaving Nodes in Mobile Ad-Hoc Networks. ICON (2007)
H. Lin, José G. Delgado-Frias, Sirisha Medidi
Using a cache scheme to detect selfish nodes in mobile ad hoc networks. Communications, Internet, and Information Technology (2007)
R. Guo, José G. Delgado-Frias
A novel compaction scheme for routing tables in TCAM to enhance cache hit rate. Communications, Internet, and Information Technology (2007)
Daniel R. Blum, José G. Delgado-Frias
Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories. ISCAS (2007)
Peter Sapaty, Masanori Sugisaka, Robert Finkelstein, José G. Delgado-Frias, Nikolay N. Mirenkov
Emergent societies: advanced IT support of crisis relief missions. Artif. Life Robotics 11 (1) (2007)
Suryanarayana Tatapudi, José G. Delgado-Frias
A mesochronous pipelining scheme for high-performance digital systems. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2006)
Li Zhao, José G. Delgado-Frias
On Throughput of Multipath Data Transmission over Multihop Ad Hoc Networks. Wireless and Optical Communications (2006)
Suryanarayana Tatapudi, José G. Delgado-Frias
A mesochronous pipeline scheme for high performance low power digital systems. ISCAS (2006)
Rongsen He, José G. Delgado-Frias
Interleaved Multistage Switching Fabrics for Scalable High Performance Routers. GLOBECOM (2006)
Li Zhao, José G. Delgado-Frias
Multipath Routing Based Secure Data Transmission in Ad Hoc Networks. WiMob (2006)
Li Zhao, José G. Delgado-Frias
Performance Analysis of Multipath Data Transmission in Multihop Ad Hoc Networks. SECON (2006)
Mitchell J. Myjak, José G. Delgado-Frias
Superpipelined reconfigurable hardware for DSP. ISCAS (2006)
Mitchell J. Myjak, Jonathan Larson, José G. Delgado-Frias
Mapping and Performance of DSP Benchmarks on a Medium-Grain Reconfigurable Architecture. ERSA (2006)
José G. Delgado-Frias, Jabulani Nyathi, Suryanarayana Tatapudi
Decoupled dynamic ternary content addressable memories. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2005)
Suryanarayana Tatapudi, José G. Delgado-Frias
A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme. CDES (2005)
Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias
A distributed FIFO scheme for on chip communication. ISCAS (2) (2005)
Jin Liu, José G. Delgado-Frias
DAMQ Self-Compacting Buffer Schemes for Systems with Network-On-Chip. CDES (2005)
Daniel R. Blum, Mitchell J. Myjak, José G. Delgado-Frias
Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS. CDES (2005)
Suryanarayana Tatapudi, José G. Delgado-Frias
A High Performance Hybrid Wave-Pipelined Multiplier. ISVLSI (2005)
Mitchell J. Myjak, José G. Delgado-Frias
A Symmetric Differential Clock Generator for Bit-Serial Hardware. CDES (2005)
Mitchell J. Myjak, Fredrick L. Anderson, José G. Delgado-Frias
H-Tree Interconnection Structure for Reconfigurable DSP Hardware. ERSA (2004)
Andy Widjaja, José G. Delgado-Frias
An H-Tree Based Configuration Scheme for Reconfigurable DSP Hardware. ESA/VLSI (2004)
Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias
A Distributed FIFO Scheme for System on Chip Inter-Component Communication. ESA/VLSI (2004)
Mitchell J. Myjak, José G. Delgado-Frias
Pipelined Multipliers for Reconfigurable Hardware. IPDPS (2004)
Mitchell J. Myjak, José G. Delgado-Frias
A Two-Level Reconfigurable Architecture for Digital Signal Processing. VLSI (2003)
Fred L. Anderson IV, José G. Delgado-Frias
A Reconfigurable Switch for a DSP Array. VLSI (2003)
Daniel R. Blum, José G. Delgado-Frias
A Fault-Tolerant Memory-Based Cell for a Reconfigurable DSP Processor. VLSI (2003)
José G. Delgado-Frias, Girish B. Ratanpal
A VLSI wrapped wave front arbiter for crossbar switches. ACM Great Lakes Symposium on VLSI (2001)
Victor A. Skormin, José G. Delgado-Frias, Dennis L. McGee, Joseph Giordano, Leonard J. Popyack, Vladimir I. Gorodetski, Alexander O. Tarakanov
BASIS: A Biological Approach to System Information Security. MMM-ACNS (2001)
José G. Delgado-Frias, Jabulani Nyathi
A wave-pipelined CMOS associate router for communication switches. ISCAS (2000)
José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan
A wave-pipelined router architecture using ternary associative memory. ACM Great Lakes Symposium on VLSI (2000)
Stamatis Vassiliadis, Ming Zhang, José G. Delgado-Frias
Elementary function generators for neural-network emulators. IEEE Trans. Neural Networks Learn. Syst. 11 (6) (2000)
Valentine C. Aikens II, José G. Delgado-Frias, Gerald G. Pechanek, Stamatis Vassiliadis
A neuro-emulator with embedded capabilities for generalized learning. J. Syst. Archit. 45 (14) (1999)
Chien-Ying Lu, José G. Delgado-Frias, Wei Lin
A Clustering and Genetic Scheme for Large Tsp Optimization Problems. Cybern. Syst. 29 (2) (1998)
José G. Delgado-Frias, Jabulani Nyathi
A VLSI High-Performance Encoder with Priority Lookahead. Great Lakes Symposium on VLSI (1998)
José G. Delgado-Frias, Richard Diaz
A VLSI Self-Compacting Buffer for DAMQ Communication Switches. Great Lakes Symposium on VLSI (1998)
Adger E. Harvin III, José G. Delgado-Frias
A Dictionary Machine Emulation on a VLSI Computing Tree System. Great Lakes Symposium on VLSI (1998)
Douglas H. Summerville, José G. Delgado-Frias
Approaches for determining dynamic synchronization resource requirements. CATA (1998)
Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis
Executing tree routing algorithms on a high-performance pattern associative router. J. Syst. Archit. 44 (11) (1998)
Valentine C. Aikens II, José G. Delgado-Frias, Steven M. Barber, Gerald G. Pechanek, Stamatis Vassiliadis
A neuro-emulator with learning and virtual emulation capabilities. ICNN (1996)
Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis
A Flexible Bit-Pattern Associative Router for Interconnection Networks. IEEE Trans. Parallel Distributed Syst. 7 (5) (1996)
José G. Delgado-Frias, Jabulani Nyathi, Chester L. Miller, Douglas H. Summerville
A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh. Great Lakes Symposium on VLSI (1996)
Ming Zhang, Stamatis Vassiliadis, José G. Delgado-Frias
Sigmoid Generators for Neural Computing Using Piecewise Approximations. IEEE Trans. Computers 45 (9) (1996)
George Triantafyllos, Stamatis Vassiliadis, José G. Delgado-Frias
Software Metrics and Microcode: A Case Study. J. Softw. Maintenance Res. Pract. 8 (3) (1996)
Daniel G. Rice, José G. Delgado-Frias, Douglas H. Summerville
A Pattern-Associative Router for Interconnection Network Adaptive Algorithms. Euro-Par, Vol. I (1996)
Valentine C. Aikens II, Steven M. Barber, José G. Delgado-Frias, Gerald G. Pechanek, Stamatis Vassiliadis
A Neuro-Architecture with Embedded Learning. Parallel and Distributed Computing and Systems (1995)
Daniel G. Rice, José G. Delgado-Frias, Douglas H. Summerville
A Pattern-Associative Router for Adaptive Algorithms in Hypercube Networks. Parallel and Distributed Computing and Systems (1995)
Joonho Park, Stamatis Vassiliadis, José G. Delgado-Frias
Flexible oblivious router architecture. IBM J. Res. Dev. 39 (3) (1995)
Adger E. Harvin III, José G. Delgado-Frias
A VLSI-Processing and Communicating Pipelined Tree for Parallel Computing. Parallel and Distributed Computing and Systems (1995)
Weili Chu, Stamatis Vassiliadis, José G. Delgado-Frias
The multi-associative branch target buffer: a cost effective BTB mechanism. Microprocess. Microprogramming 41 (3) (1995)
Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis
A High Performance Pattern Associative Oblivious Router for Tree Topologies. IPPS (1994)
Chuan-Jen Chang, Stamatis Vassiliadis, José G. Delgado-Frias
An investigation of binary CLA and ripple CMOS adder designs. Microprocess. Microprogramming 40 (1) (1994)
Joonho Park, Brian W. O'Krafka, Stamatis Vassiliadis, José G. Delgado-Frias
Design and evaluation of a DAMQ multiprocessor network with self-compacting buffers. SC (1994)
José G. Delgado-Frias, Rovy Sze, Douglas H. Summerville, Valentine C. Aikens II
A VLSI CAM-based flexible oblivious router for multiprocessor interconnection networks. Great Lakes Symposium on VLSI (1994)
Gerald G. Pechanek, José G. Delgado-Frias, Stamatis Vassiliadis
A massively parallel diagonal-fold array processor. ASAP (1993)
Stamatis Vassiliadis, Gerald G. Pechanek, José G. Delgado-Frias
Spin: the Sequential Pipelined Neuroemulator. Int. J. Artif. Intell. Tools 2 (1) (1993)
Gerald G. Pechanek, Stamatis Vassiliadis, José G. Delgado-Frias
Digital neural emulators using tree accumulation and communication structures. IEEE Trans. Neural Networks 3 (6) (1992)
José G. Delgado-Frias, Stamatis Vassiliadis, Jamshid Goshtasbi
Semantic Network Architectures: an Evaluation. Int. J. Artif. Intell. Tools 1 (1) (1992)

José G. Delgado-Frias.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

José G. Delgado-Frias