A Fault-Tolerant Memory-Based Cell for a Reconfigurable DSP Processor.
Daniel R. BlumJosé G. Delgado-FriasPublished in: VLSI (2003)
Keyphrases
- fault tolerant
- systolic array
- digital signal
- fault tolerance
- data flow
- parallel architecture
- distributed systems
- high speed
- interconnection networks
- signal processing
- state machine
- load balancing
- low cost
- safety critical
- mobile agent system
- functional units
- hardware implementation
- digital signal processing
- high availability
- shared memory
- real time
- parallel processing
- response time
- image processing
- artificial intelligence