Login / Signup

FPGA schemes for minimizing the power-throughput trade-off in executing the Advanced Encryption Standard algorithm.

Jason Van DykenJosé G. Delgado-Frias
Published in: J. Syst. Archit. (2010)
Keyphrases
  • trade off
  • hardware implementation
  • recognition algorithm
  • advanced encryption standard
  • digital libraries
  • response time
  • power consumption