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A VLSI CAM-based flexible oblivious router for multiprocessor interconnection networks.
José G. Delgado-Frias
Rovy Sze
Douglas H. Summerville
Valentine C. Aikens II
Published in:
Great Lakes Symposium on VLSI (1994)
Keyphrases
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interconnection networks
network on chip
fault tolerant
parallel algorithm
multistage
signal processing
routing algorithm
message passing
bayesian networks
distributed systems
end to end