A Two-Level Reconfigurable Architecture for Digital Signal Processing.

Mitchell J. Myjak José G. Delgado-Frias

Published in: VLSI (2003)

Keyphrases

digital signal processing
reconfigurable architecture
data flow
systolic array
signal processing
image processing
low power
computer vision and image processing
high speed
real time
computer vision
three dimensional
high quality
probabilistic model
field programmable gate array