Olivier Muller

Publication Activity (10 Years)

Years Active: 2006-2023
Publications (10 Years): 17

Top Topics

Resource Constraints

Hardware Implementation

Knowledge Transfer

Hardware Designs

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Bruno Ferres, Olivier Muller, Frédéric Rousseau
A Chisel Framework for Flexible Design Space Exploration through a Functional Approach. CoRR (2023)
Bruno Ferres, Olivier Muller, Frédéric Rousseau
A Chisel Framework for Flexible Design Space Exploration through a Functional Approach. ACM Trans. Design Autom. Electr. Syst. 28 (4) (2023)
Riccardo Tenderini, Federico Betti, Ortal Yona Senouf, Olivier Muller, Simone Deparis, Annalisa Buffa, Emmanuel Abbe
Can Knowledge Transfer Techniques Compensate for the Limited Myocardial Infarction Data by Leveraging Hæmodynamics? An in silico Study. AIME (2023)
Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groléat, Frédéric Pétrot
Toward Agile Hardware Designs With Chisel: A Network Use Case. IEEE Des. Test 39 (1) (2022)
Bruno Ferres, Olivier Muller, Frédéric Rousseau
Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration. RSP (2021)
Arif Sasongko, I. M. Narendra Kumara, Arief Wicaksana, Frédéric Rousseau, Olivier Muller
Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple Streams. ACM Trans. Reconfigurable Technol. Syst. 14 (3) (2021)
Bruno Ferres, Olivier Muller, Frédéric Rousseau
Chisel Usecase: Designing General Matrix Multiply for FPGA. ARC (2020)
Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groléat, Frédéric Pétrot
(System)Verilog to Chisel Translation for Faster Hardware Design. RSP (2020)
Olivier Muller, Adrien Prost-Boucle, Alban Bourge, Frédéric Pétrot
Efficient Decompression of Binary Encoded Balanced Ternary Sequences. IEEE Trans. Very Large Scale Integr. Syst. 27 (8) (2019)
Georgios Christodoulis, François Broquedis, Olivier Muller, Manuel Selva, Frederic Desprez
An FPGA target for the StarPU heterogeneous runtime system. ReCoSoC (2018)
Thomas Baumela, Olivier Gruber, Olivier Muller, Frédéric Pétrot
Message-Oriented Devices on FPGAs. RSP (2018)
Arief Wicaksana, Alban Bourge, Olivier Muller, Arif Sasongko, Frédéric Rousseau
Prototyping dynamic task migration on heterogeneous reconfigurable systems. RSP (2017)
Simon Pontie, Alban Bourge, Adrien Prost-Boucle, Paolo Maistri, Olivier Muller, Régis Leveugle, Frédéric Rousseau
HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic. DSD (2016)
Arief Wicaksana, Adrien Prost-Boucle, Olivier Muller, Frédéric Rousseau, Arif Sasongko
On-board non-regression test of HLS tools targeting FPGA. RSP (2016)
Alban Bourge, Olivier Muller, Frédéric Rousseau
Generating Efficient Context-Switch Capable Circuits through Autonomous Design Flow. ACM Trans. Reconfigurable Technol. Syst. 10 (1) (2016)
Arief Wicaksana, Alban Bourge, Olivier Muller, Frédéric Rousseau
Demonstration of a context-switch method for heterogeneous reconfigurable systems. CoRR (2016)
Arief Wicaksana, Alban Bourge, Olivier Muller, Frédéric Rousseau
Demonstration of a context-switch method for heterogeneous reconfigurable systems. FPL (2016)
Alban Bourge, Olivier Muller, Frédéric Rousseau
Automatic High-Level Hardware Checkpoint Selection for Reconfigurable Systems. FCCM (2015)
Alban Bourge, Olivier Muller, Frédéric Rousseau
A Novel Method for Enabling FPGA Context-Switch (Abstract Only). FPGA (2015)
Adrien Prost-Boucle, Olivier Muller, Frédéric Rousseau
Fast and standalone Design Space Exploration for High-Level Synthesis under resource constraints. J. Syst. Archit. 60 (1) (2014)
Adrien Prost-Boucle, Olivier Muller, Frédéric Rousseau
A Fast and Autonomous HLS Methodology for Hardware Accelerator Generation under Resource Constraints. DSD (2013)
Yan Xu, Olivier Muller, Pierre-Henri Horrein, Frédéric Pétrot
HCM: An abstraction layer for seamless programming of DPR FPGA. FPL (2012)
Olivier Muller, Amer Baghdadi, Michel Jézéquel
Parallelism Efficiency in Convolutional Turbo Decoding. EURASIP J. Adv. Signal Process. 2010 (2010)
Olivier Muller, Amer Baghdadi, Michel Jézéquel
From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding. IEEE Trans. Very Large Scale Integr. Syst. 17 (1) (2009)
Olivier Muller, Amer Baghdadi, Michel Jézéquel
From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding. IEEE International Workshop on Rapid System Prototyping (2008)
Hazem Moussa, Olivier Muller, Amer Baghdadi, Michel Jézéquel
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding. DATE (2007)
Olivier Muller, Amer Baghdadi, Michel Jézéquel
On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference. GLOBECOM (2006)
Olivier Muller, Amer Baghdadi, Michel Jézéquel
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding. DATE (2006)