Arief Wicaksana

Publication Activity (10 Years)

Years Active: 2011-2022
Publications (10 Years): 9

Top Topics

Design Space Exploration

Memory Hierarchy

Hardware Software Co Design

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

DroneSE/RAPIDO@HiPEAC

Publications

Fatma Jebali, Oumaima Matoussi, Arief Wicaksana, Amir Charif, Lilia Zaourar
Decoupling processor and memory hierarchy simulators for efficient design space exploration. DroneSE/RAPIDO@HiPEAC (2022)
Arif Sasongko, I. M. Narendra Kumara, Arief Wicaksana, Frédéric Rousseau, Olivier Muller
Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple Streams. ACM Trans. Reconfigurable Technol. Syst. 14 (3) (2021)
Cinzia Bernardeschi, Andrea Domenici, Maurizio Palmieri, Sergio Saponara, Tanguy Sassolas, Arief Wicaksana, Lilia Zaourar
Cross-level Co-simulation and Verification of an Automatic Transmission Control on Embedded Processor. SEFM (2020)
Arief Wicaksana, Amir Charif, Caaliph Andriamisaina, Nicolas Ventroux
Hybrid Prototyping Methodology for Rapid System Validation in HW/SW Co-Design. DASIP (2019)
Arief Wicaksana, Alban Bourge, Olivier Muller, Arif Sasongko, Frédéric Rousseau
Prototyping dynamic task migration on heterogeneous reconfigurable systems. RSP (2017)
Arief Wicaksana, Arif Sasongko
Fast and reconfigurable packet classification engine in FPGA-based firewall. CoRR (2016)
Arief Wicaksana, Adrien Prost-Boucle, Olivier Muller, Frédéric Rousseau, Arif Sasongko
On-board non-regression test of HLS tools targeting FPGA. RSP (2016)
Arief Wicaksana, Alban Bourge, Olivier Muller, Frédéric Rousseau
Demonstration of a context-switch method for heterogeneous reconfigurable systems. CoRR (2016)
Arief Wicaksana, Alban Bourge, Olivier Muller, Frédéric Rousseau
Demonstration of a context-switch method for heterogeneous reconfigurable systems. FPL (2016)
Arief Wicaksana, Arif Sasongko
Fast and reconfigurable packet classification engine in FPGA-based firewall. ICEEI (2011)