Eslam Yahya

Publication Activity (10 Years)

Years Active: 2003-2018
Publications (10 Years): 6

Top Topics

Processing Pipeline

Distortion Correction

Delay Insensitive

Asynchronous Circuits

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Shady O. Agwa, Eslam Yahya, Yehea Ismail
A Low Power Self-healing Resilient Microarchitecture for PVT Variability Mitigation. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2018)
Shady O. Agwa, Eslam Yahya, Yehea Ismail
Power efficient AES core for IoT constrained devices implemented in 130nm CMOS. ISCAS (2017)
Nada El-meligy, Moustafa Amin, Eslam Yahya, Yehea Ismail
130nm Low power asynchronous AES core. ISCAS (2017)
Eslam Amr, Marina Maher, Amir Rashad, Mohamed Raafat, Yosif Diaa, Eslam Yahya, Yehea Ismail
Presenting a synchronous - Asynchronous standard cell library based on 7nm FinFET technology. ICM (2016)
Tarek Ramadan, Eslam Yahya, Mohamed Dessouky, Yehea Ismail
Accuracy-improved coupling capacitance model for through-silicon via (TSV) arrays using dimensional analysis. ISCAS (2016)
Shady O. Agwa, Eslam Yahya, Yehea Ismail
ERSUT: A Self-Healing Architecture for Mitigating PVT Variations Without Pipeline Flushing. IEEE Trans. Circuits Syst. II Express Briefs (11) (2016)
Eslam Yahya, Hatem Zakaria, Yehea Ismail
Deadlock detection in conditional asynchronous circuits under mismatched branch selection. ICECS (2015)
Tarek Ramadan, Eslam Yahya, Mohamed Dessouky, Yehea I. Ismail
Coupling capacitance extraction in through-silicon via (TSV) arrays. ICECS (2015)
Karim Ali, Eslam Yahya, Alaa B. El-Rouby, Yehea I. Ismail
Library based macro-modeling methodology for Through Silicon Via (TSV) arbitrary arrays. Microelectron. J. 46 (12) (2015)
Kareem Ali, Eslam Yahya, Alaa B. El-Rouby, Yehea Ismail
Different scenarios for estimating coupling capacitances of through silicon via (TSV) arrays. ICEAC (2015)
Eslam Yahya, Laurent Fesquet, Yehea I. Ismail, Marc Renaudin
Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation. ASYNC (2013)
Shady O. Agwa, Eslam Yahya, Yehea I. Ismail
Variability mitigation using correction function technique. ICECS (2013)
Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet
Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case. PATMOS (2010)
Oussama Elissati, Sébastien Rieubon, Eslam Yahya, Laurent Fesquet
Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks. VLSI-SoC (Selected Papers) (2010)
Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet
A high-speed high-resolution low-phase noise oscillator using self-timed rings. VLSI-SoC (2010)
Eslam Yahya, Laurent Fesquet
Asynchronous design: A promising paradigm for electronic circuits and systems. ICECS (2009)
Eslam Yahya, Oussama Elissati, Hatem Zakaria, Laurent Fesquet, Marc Renaudin
Programmable/Stoppable Oscillator Based on Self-Timed Rings. ASYNC (2009)
Eslam Yahya, Marc Renaudin
Asynchronous Linear Pipelines: An efficient-optimal pipelining algorithm. ICECS (2008)
Eslam Yahya, Marc Renaudin
Performance Modeling and Analysis of Asynchronous Linear-Pipeline with Time Variable Delays. ICECS (2007)
Eslam Yahya, Marc Renaudin
QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis. PATMOS (2006)
François Charot, Eslam Yahya, Charles Wagner
Efficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGA. FPL (2003)