Efficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGA.

François Charot Eslam Yahya Charles Wagner

Published in: FPL (2003)

Keyphrases

hardware implementation
hardware design
field programmable gate array
software implementation
computationally expensive
efficient implementation
high speed
cost effective
programmable logic
real time
neural network
learning algorithm
image processing
signal processing
lightweight
parallel architecture