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Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems.
Jean-Baptiste Rigaud
Jerome Quartana
Laurent Fesquet
Marc Renaudin
Published in:
VLSI-SOC (2001)
Keyphrases
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communication systems
information processing systems
functional verification
low cost
single chip
evolvable hardware
multiple access
design process
query processing
high speed
computer systems
wireless networks
communication technologies
channel estimation
high level synthesis
blind equalization