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Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals.
G. Fraidy Bouesse
Marc Renaudin
Gilles Sicard
Published in:
VLSI-SoC (2005)
Keyphrases
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delay insensitive
asynchronous circuits
signal processing
low power
countermeasures
database
data sets
neural network
image processing
differential power analysis