Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits.
Aymane BouzafourMarc RenaudinHubert GaravelRadu MateescuWendelin SerwePublished in: ASYNC (2018)
Keyphrases
- asynchronous circuits
- model checking
- temporal logic
- process algebra
- delay insensitive
- finite state
- formal verification
- temporal properties
- formal specification
- automated verification
- computation tree logic
- model checker
- symbolic model checking
- partial order reduction
- transition systems
- bounded model checking
- reachability analysis
- finite state machines
- verification method
- concurrent systems
- pspace complete
- timed automata
- epistemic logic
- formal methods
- deterministic finite automaton
- distributed systems
- artificial intelligence