Formal Verification of C-element Circuits.

Chao Yan Florent Ouchet Laurent Fesquet Katell Morin-Allory

Published in: ASYNC (2011)

Keyphrases

formal verification
model checking
model checker
automated verification
bounded model checking
high speed
symbolic model checking
analog circuits
logic synthesis
temporal logic
digital circuits
asynchronous circuits
electronic circuits
delay insensitive