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Comparison of low-voltage scaling in synchronous and asynchronous FD-SOI circuits.
Thiago Ferreira de Paiva Leite
Rodrigo Possamai Bastos
Rodrigo Iga Jadue
Laurent Fesquet
Published in:
PATMOS (2016)
Keyphrases
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low voltage
cmos technology
design considerations
random access memory
power line
high speed
silicon on insulator
sensor networks