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On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs.
Leonardo Bonet Zordan
Alberto Bosio
Luigi Dilillo
Patrick Girard
Aida Todri
Arnaud Virazel
Nabil Badereddine
Published in:
ITC (2013)
Keyphrases
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low power
high speed
logic circuits
power consumption
vlsi circuits
low cost
power reduction
cmos technology
power dissipation
mixed signal
delay insensitive
high power
single chip
low power consumption
wireless transmission
digital signal processing
vlsi architecture
power saving