Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults.
Imran WaliArnaud VirazelAlberto BosioLuigi DililloPatrick GirardAida TodriPublished in: DDECS (2014)
Keyphrases
- fault diagnosis
- fault detection
- processor core
- steady state
- instruction set
- high speed
- multiple faults
- level parallelism
- access control
- fault model
- special purpose hardware
- instruction set architecture
- floating point
- design methodology
- model based diagnosis
- data flow
- circuit design
- embedded dram
- operating system
- fault identification
- test cases
- fault detection and isolation
- multi core processors
- physical design
- functional verification
- multi core systems
- markov chain
- root cause
- object oriented