Zdenek Vasícek

ORCID

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 67

Top Venues

Brno University of Technology, Czech Republic (PHD)

Education History

Brno University of Technology, Czech Republic

PHD

Publications

Zdenek Vasícek
Automated Synthesis of Commutative Approximate Arithmetic Operators. CEC (2024)
Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. CoRR (2024)
Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. DATE (2024)
Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. DDECS (2024)
Vojtech Mrazek, Argyris Kokkinis, Panagiotis Papanikolaou, Zdenek Vasícek, Kostas Siozios, Georgios Tzimpragos, Mehdi Baradaran Tahoori, Georgios Zervakis
Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks. CoRR (2024)
Michal Pinos, Vojtech Mrazek, Filip Vaverka, Zdenek Vasícek, Lukás Sekanina
Acceleration Techniques for Automated Design of Approximate Convolutional Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 13 (1) (2023)
Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. CoRR (2023)
Roman Kalkreuth, Zdenek Vasícek, Jakub Husa, Diederick Vermetten, Furong Ye, Thomas Bäck
General Boolean Function Benchmark Suite. FOGA (2023)
Roman Kalkreuth, Zdenek Vasícek, Jakub Husa, Diederick Vermetten, Furong Ye, Thomas Bäck
Towards a General Boolean Function Benchmark Suite. GECCO Companion (2023)
Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. ICCAD (2023)
Roman Kalkreuth, Léo Françoso Dal Piccol Sotto, Zdenek Vasícek
Graph-based genetic programming. GECCO Companion (2022)
Jitka Kocnová, Zdenek Vasícek
Delay-aware evolutionary optimization of digital circuits. ISVLSI (2022)
Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
SagTree: Towards efficient mutation in evolutionary circuit approximation. Swarm Evol. Comput. 69 (2022)
Zdenek Vasícek
Synthesis of approximate circuits for LUT-based FPGAs. DDECS (2021)
Jitka Kocnová, Zdenek Vasícek
Resynthesis of logic circuits using machine learning and reconvergent paths. DSD (2021)
David Hodan, Vojtech Mrazek, Zdenek Vasícek
Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. Genet. Program. Evolvable Mach. 22 (4) (2021)
Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek
Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. CoRR (2020)
Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek
Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 10 (4) (2020)
David Hodan, Vojtech Mrazek, Zdenek Vasícek
Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. GECCO (2020)
Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. DAC (2020)
Jitka Kocnová, Zdenek Vasícek
EA-based resynthesis: an efficient tool for optimization of digital circuits. Genet. Program. Evolvable Mach. 21 (3) (2020)
Alberto Bosio, Stefano Di Carlo, Patrick Girard, Ernesto Sánchez, Alessandro Savino, Lukás Sekanina, Marcello Traiola, Zdenek Vasícek, Arnaud Virazel
Design, Verification, Test and In-Field Implications of Approximate Computing Systems. ETS (2020)
Filip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. CoRR (2020)
Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
Adaptive verifiability-driven strategy for evolutionary approximation of arithmetic circuits. Appl. Soft Comput. 95 (2020)
David Hodan, Vojtech Mrazek, Zdenek Vasícek
Semantically-Oriented Mutation Operator in Cartesian Genetic Programming for Evolutionary Circuit Design. CoRR (2020)
Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
Adaptive Verifiability-Driven Strategy for Evolutionary Approximation of Arithmetic Circuits. CoRR (2020)
Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. CoRR (2020)
Mohammad Saeed Ansari, Vojtech Mrazek, Bruce F. Cockburn, Lukás Sekanina, Zdenek Vasícek, Jie Han
Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 28 (2) (2020)
Filip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. DATE (2020)
Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek
Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. AICAS (2020)
Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique
ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. CoRR (2019)
Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. DAC (2019)
Jitka Kocnová, Zdenek Vasícek
Towards a Scalable EA-Based Optimization of Digital Circuits. EuroGP (2019)
Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique
ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. ICCAD (2019)
Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. CoRR (2019)
Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
Automated Circuit Approximation Method Driven by Data Distribution. CoRR (2019)
Zdenek Vasícek
Formal Methods for Exact Analysis of Approximate Circuits. IEEE Access 7 (2019)
Jitka Kocnová, Zdenek Vasícek
Impact of subcircuit selection on the efficiency of CGP-based optimization of gate-level circuits. GECCO (Companion) (2019)
Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
Automated Circuit Approximation Method Driven by Data Distribution. DATE (2019)
Jitka Kocnová, Zdenek Vasícek
EA-Based Refactoring of Mapped Logic Circuits. ISCAS (2019)
Lukás Sekanina, Vojtech Mrazek, Zdenek Vasícek
Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. ICECS (2018)
Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
ADAC: Automated Design of Approximate Circuits. CAV (1) (2018)
Vojtech Mrazek, Zdenek Vasícek, Radek Hrbacek
Role of circuit representation in evolutionary design of energy-efficient approximate circuits. IET Comput. Digit. Tech. 12 (4) (2018)
Lukás Sekanina, Zdenek Vasícek, Alberto Bosio, Marcello Traiola, Paolo Rech, Daniel Oliveira, Fernando Fernandes, Stefano Di Carlo
Special session: How approximate computing impacts verification, test and reliability. VTS (2018)
Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. AHS (2018)
Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Honglan Jiang, Jie Han
Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error. IEEE Trans. Very Large Scale Integr. Syst. 26 (11) (2018)
Vojtech Mrazek, Marek Sýs, Zdenek Vasícek, Lukás Sekanina, Vashek Matyas
Evolving boolean functions for fast and efficient randomness testing. GECCO (2018)
Vojtech Mrazek, Zdenek Vasícek
Evolutionary design of large approximate adders optimized for various error criteria. GECCO (Companion) (2018)
Vojtech Mrazek, Zdenek Vasícek
Parallel optimization of transistor level circuits using cartesian genetic programming. GECCO (Companion) (2017)
Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished. ICCAD (2017)
Zdenek Vasícek, Vojtech Mrazek
Trading between quality and non-functional properties of median filter in embedded systems. Genet. Program. Evolvable Mach. 18 (1) (2017)
Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
Towards low power approximate DCT architecture for HEVC standard. DATE (2017)
Muhammad Shafique, Rehan Hafiz, Muhammad Usama Javed, Sarmad Abbas, Lukás Sekanina, Zdenek Vasícek, Vojtech Mrazek
Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. ISVLSI (2017)
Vojtech Mrazek, Radek Hrbacek, Zdenek Vasícek, Lukás Sekanina
EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. DATE (2017)
Zdenek Vasícek, Lukás Sekanina
Evolutionary design of complex approximate combinational circuits. Genet. Program. Evolvable Mach. 17 (2) (2016)
Vojtech Mrazek, Zdenek Vasícek
Automatic design of arbitrary-size approximate sorting networks with error guarantee. PATMOS (2016)
Zdenek Vasícek, Lukás Sekanina
Search-based synthesis of approximate circuits implemented into FPGAs. FPL (2016)
Vojtech Mrazek, Syed Shakib Sarwar, Lukás Sekanina, Zdenek Vasícek, Kaushik Roy
Design of power-efficient approximate multipliers for approximate artificial neural networks. ICCAD (2016)
Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
Evolutionary functional approximation of circuits implemented into FPGAs. SSCI (2016)
Radek Hrbacek, Vojtech Mrazek, Zdenek Vasícek
Automatic design of approximate circuits by means of multi-objective evolutionary algorithms. DTIS (2016)
Zdenek Vasícek
Cartesian GP in Optimization of Combinational Circuits with Hundreds of Inputs and Thousands of Gates. EuroGP (2015)
Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
Evolutionary Approximation of Software for Embedded Systems: Median Function. GECCO (Companion) (2015)
Vojtech Mrazek, Zdenek Vasícek
Evolutionary Design of Transistor Level Digital Circuits Using Discrete Simulation. EuroGP (2015)
Zdenek Vasícek, Lukás Sekanina
Evolutionary Approach to Approximate Digital Circuits Design. IEEE Trans. Evol. Comput. 19 (3) (2015)
Vojtech Mrazek, Zdenek Vasícek
Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers. EUC (2015)
Zdenek Vasícek, Lukás Sekanina
Evolutionary Approximation of Complex Digital Circuits. GECCO (Companion) (2015)
Zdenek Vasícek, Lukás Sekanina
Circuit Approximation Using Single- and Multi-objective Cartesian GP. EuroGP (2015)
Zdenek Vasícek, Lukás Sekanina
Evolutionary design of approximate multipliers under different error metrics. DDECS (2014)
Lukás Sekanina, Ondrej Ptak, Zdenek Vasícek
Cartesian genetic programming as local optimizer of logic networks. IEEE Congress on Evolutionary Computation (2014)
Lukás Sekanina, Zdenek Vasícek
On Evolutionary Approximation of Logic Circuits. Computing with New Resources (2014)
Zdenek Vasícek, Michal Bidlo
On Evolution of Multi-category Pattern Classifiers Suitable for Embedded Systems. EuroGP (2014)
Vojtech Mrazek, Zdenek Vasícek
Acceleration of transistor-level evolution using Xilinx Zynq Platform. ICES (2014)
Zdenek Vasícek, Lukás Sekanina
How to evolve complex combinational circuits from scratch? ICES (2014)
Michal Bidlo, Zdenek Vasícek
Functional-level development of image filters by means of cellular automata. ICES (2013)
Zdenek Vasícek, Michal Bidlo, Lukás Sekanina
Evolution of efficient real-time non-linear image filters for FPGAs. Soft Comput. 17 (11) (2013)
Lukás Sekanina, Zdenek Vasícek
Approximate circuit design by means of evolvable hardware. ICES (2013)
Michal Bidlo, Zdenek Vasícek
Evolution of cellular automata with conditionally matching rules. IEEE Congress on Evolutionary Computation (2013)
Lukás Sekanina, Richard Ruzicka, Zdenek Vasícek, Václav Simek, Petr Hanácek
Implementing A Unique Chip Id On A Reconfigurable Polymorphic Circuit. Inf. Technol. Control. 42 (1) (2013)
Lukás Sekanina, Vojtech Salajka, Zdenek Vasícek
Two-step evolution of polymorphic circuits for image multi-filtering. IEEE Congress on Evolutionary Computation (2012)
Michal Bidlo, Zdenek Vasícek
Cellular Automaton as Sorting Network Generator Using Instruction-Based Development. ACRI (2012)
Lukás Sekanina, Zdenek Vasícek
A SAT-based fitness function for evolutionary optimization of polymorphic circuits. DATE (2012)
Zdenek Vasícek, Karel Slaný
Efficient Phenotype Evaluation in Cartesian Genetic Programming. EuroGP (2012)
Michal Bidlo, Zdenek Vasícek
Evolution of cellular automata using instruction-based approach. IEEE Congress on Evolutionary Computation (2012)
Zdenek Vasícek, Lukás Sekanina
On area minimization of complex combinational circuits using cartesian genetic programming. IEEE Congress on Evolutionary Computation (2012)
Zdenek Vasícek, Lukás Sekanina
Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware. Genet. Program. Evolvable Mach. 12 (3) (2011)
Zdenek Vasícek, Michal Bidlo, Lukás Sekanina, Kyrre Glette
Evolutionary design of efficient and robust switching image filters. AHS (2011)
Zdenek Vasícek, Lukás Sekanina
A global postsynthesis optimization method for combinational circuits. DATE (2011)
Zdenek Vasícek, Michal Bidlo
Evolutionary design of robust noise-specific image filters. IEEE Congress on Evolutionary Computation (2011)
Petr Fiser, Jan Schmidt, Zdenek Vasícek, Lukás Sekanina
On logic synthesis of conventionally hard to synthesize circuits using genetic programming. DDECS (2010)
Michal Bidlo, Zdenek Vasícek, Karel Slaný
Sorting Network Development Using Cellular Automata. ICES (2010)
Zdenek Vasícek, Lukás Sekanina, Michal Bidlo
A method for design of impulse bursts noise filters optimized for FPGA implementations. DATE (2010)
Michal Bidlo, Zdenek Vasícek
Comparison of the Uniform and Non-Uniform Cellular Automata-Based Approach to the Development of Combinational Circuits. AHS (2009)
Lukás Sekanina, Richard Ruzicka, Zdenek Vasícek, Roman Prokop, Lukás Fujcik
REPOMO32 - New reconfigurable polymorphic integrated circuit for adaptive hardware. WEAH (2009)
Michal Bidlo, Zdenek Vasícek
Investigating gate-level evolutionary development of combinational multipliers using enhanced cellular automata-based model. IEEE Congress on Evolutionary Computation (2009)
Zdenek Vasícek, Michal Bidlo, Lukás Sekanina, Jim Tørresen, Kyrre Glette, Marcus Furuholmen
Evolution of Impulse Bursts Noise Filters. AHS (2009)
Michal Bidlo, Zdenek Vasícek
Development of combinational circuits using non-uniform cellular automata: initial results. GECCO (2009)
Michal Bidlo, Zdenek Vasícek
Gate-Level Evolutionary Development Using Cellular Automata. AHS (2008)
Zdenek Vasícek, Lukás Sekanina
Hardware Accelerators for Cartesian Genetic Programming. EuroGP (2008)
Zdenek Vasícek, Ladislav Capka, Lukás Sekanina
Analysis of Reconfiguration Options for a Reconfigurable Polymorphic Circuit. AHS (2008)
Zdenek Vasícek, Lukás Sekanina
Novel Hardware Implementation of Adaptive Median Filters. DDECS (2008)

Zdenek Vasícek.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Zdenek Vasícek