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Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators.
Jan Klhufek
Miroslav Safar
Vojtech Mrazek
Zdenek Vasícek
Lukás Sekanina
Published in:
DDECS (2024)
Keyphrases
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neural network
computing systems
single chip
computing platform
field programmable gate array
real time
low cost
back propagation
hardware and software
multi layer
graphics processing units
artificial neural networks
neural network is trained
computer systems
associative memory
quantization error
vlsi implementation
ibm power processor
prediction model
recurrent neural networks
multilayer perceptron
neural network model
fuzzy logic
pattern recognition
hidden layer
massively parallel
self organizing maps
data processing
high end
control system
genetic algorithm