Vojtech Mrazek

Publication Activity (10 Years)

Years Active: 2014-2023
Publications (10 Years): 71

Top Topics

Evolutionary Design

Functional Properties

Embedded Systems

Top Venues

Publications

Michal Pinos, Vojtech Mrazek, Filip Vaverka, Zdenek Vasícek, Lukás Sekanina
Acceleration Techniques for Automated Design of Approximate Convolutional Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 13 (1) (2023)
Martin Hurta, Vojtech Mrazek, Michaela Drahosova, Lukás Sekanina
MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. DDECS (2023)
Michal Pinos, Vojtech Mrazek, Lukás Sekanina
Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits. DDECS (2023)
Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. CoRR (2023)
Martin Hurta, Vojtech Mrazek, Michaela Drahosova, Lukás Sekanina
ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. DATE (2023)
Vojtech Mrazek
Approximation of Hardware Accelerators driven by Machine-Learning Models : (Embedded Tutorial). DDECS (2023)
Vojtech Mrazek, Soyiba Jawed, Muhammad Arif, Aamir Saeed Malik
Effective EEG Feature Selection for Interpretable MDD (Major Depressive Disorder) Classification. GECCO (2023)
Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. ICCAD (2023)
Alberto Marchisio, Vojtech Mrazek, Andrea Massa, Beatrice Bussolino, Maurizio Martina, Muhammad Shafique
RoHNAS: A Neural Architecture Search Framework with Conjoint Optimization for Adversarial Robustness and Hardware Efficiency of Convolutional and Capsule Networks. CoRR (2022)
Jan Klhufek, Vojtech Mrazek
ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators. DDECS (2022)
Michal Pinos, Vojtech Mrazek, Lukás Sekanina
Evolutionary approximation and neural architecture search. Genet. Program. Evolvable Mach. 23 (3) (2022)
Vojtech Mrazek
Optimization of BDD-based Approximation Error Metrics Calculations. CoRR (2022)
Milan Ceska, Jirí Matyás, Vojtech Mrazek, Tomás Vojnar
Designing Approximate Arithmetic Circuits with Combined Error Constraints. DSD (2022)
Jan Klhufek, Vojtech Mrazek
ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators. CoRR (2022)
Alberto Marchisio, Vojtech Mrazek, Andrea Massa, Beatrice Bussolino, Maurizio Martina, Muhammad Shafique
RoHNAS: A Neural Architecture Search Framework With Conjoint Optimization for Adversarial Robustness and Hardware Efficiency of Convolutional and Capsule Networks. IEEE Access 10 (2022)
Vojtech Mrazek
Optimization of BDD-based Approximation Error Metrics Calculations. ISVLSI (2022)
Martin Hurta, Michaela Drahosova, Vojtech Mrazek
Evolutionary Design of Reduced Precision Preprocessor for Levodopa-Induced Dyskinesia Classifier. PPSN (1) (2022)
Milan Ceska, Jirí Matyás, Vojtech Mrazek, Tomás Vojnar
Designing Approximate Arithmetic Circuits with Combined Error Constraints. CoRR (2022)
Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
SagTree: Towards efficient mutation in evolutionary circuit approximation. Swarm Evol. Comput. 69 (2022)
Alberto Marchisio, Vojtech Mrazek, Muhammad Abdullah Hanif, Muhammad Shafique
FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 29 (4) (2021)
David Hodan, Vojtech Mrazek, Zdenek Vasícek
Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. Genet. Program. Evolvable Mach. 22 (4) (2021)
Alberto Marchisio, Vojtech Mrazek, Muhammad Abdullah Hanif, Muhammad Shafique
DESCNet: Developing Efficient Scratchpad Memories for Capsule Network Hardware. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (9) (2021)
Michal Pinos, Vojtech Mrazek, Lukás Sekanina
Evolutionary Neural Architecture Search Supporting Approximate Multipliers. CoRR (2021)
Michal Pinos, Vojtech Mrazek, Lukás Sekanina
Evolutionary Neural Architecture Search Supporting Approximate Multipliers. EuroGP (2021)
Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek
Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. CoRR (2020)
Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek
Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 10 (4) (2020)
David Hodan, Vojtech Mrazek, Zdenek Vasícek
Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. GECCO (2020)
Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. DAC (2020)
Alessio Colucci, Alberto Marchisio, Beatrice Bussolino, Vojtech Mrazek, Maurizio Martina, Guido Masera, Muhammad Shafique
A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress. CODES+ISSS (2020)
Alberto Marchisio, Vojtech Mrazek, Muhammad Abdullah Hanif, Muhammad Shafique
DESCNet: Developing Efficient Scratchpad Memories for Capsule Network Hardware. CoRR (2020)
Filip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. CoRR (2020)
Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
Adaptive verifiability-driven strategy for evolutionary approximation of arithmetic circuits. Appl. Soft Comput. 95 (2020)
David Hodan, Vojtech Mrazek, Zdenek Vasícek
Semantically-Oriented Mutation Operator in Cartesian Genetic Programming for Evolutionary Circuit Design. CoRR (2020)
Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
Adaptive Verifiability-Driven Strategy for Evolutionary Approximation of Arithmetic Circuits. CoRR (2020)
Alberto Marchisio, Andrea Massa, Vojtech Mrazek, Beatrice Bussolino, Maurizio Martina, Muhammad Shafique
NASCaps: A Framework for Neural Architecture Search to Optimize the Accuracy and Hardware Efficiency of Convolutional Capsule Networks. ICCAD (2020)
Alberto Marchisio, Vojtech Mrazek, Muhammad Abdullah Hanif, Muhammad Shafique
ReD-CaNe: A Systematic Methodology for Resilience Analysis and Design of Capsule Networks under Approximations. DATE (2020)
Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. CoRR (2020)
Milan Ceska, Jirí Matyás, Vojtech Mrazek, Tomás Vojnar
Satisfiability Solving Meets Evolutionary Optimisation in Designing Approximate Circuits. SAT (2020)
Mohammad Saeed Ansari, Vojtech Mrazek, Bruce F. Cockburn, Lukás Sekanina, Zdenek Vasícek, Jie Han
Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 28 (2) (2020)
Filip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. DATE (2020)
Alberto Marchisio, Andrea Massa, Vojtech Mrazek, Beatrice Bussolino, Maurizio Martina, Muhammad Shafique
NASCaps: A Framework for Neural Architecture Search to Optimize the Accuracy and Hardware Efficiency of Convolutional Capsule Networks. CoRR (2020)
Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek
Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. AICAS (2020)
Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique
ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. CoRR (2019)
Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. DAC (2019)
Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique
ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. ICCAD (2019)
Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. CoRR (2019)
Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
Automated Circuit Approximation Method Driven by Data Distribution. CoRR (2019)
Alberto Marchisio, Vojtech Mrazek, Muhammad Abdullah Hanif, Muhammad Shafique
ReD-CaNe: A Systematic Methodology for Resilience Analysis and Design of Capsule Networks under Approximations. CoRR (2019)
Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
Automated Circuit Approximation Method Driven by Data Distribution. DATE (2019)
Vojtech Mrazek, Lukás Sekanina, Roland Dobai, Marek Sýs, Petr Svenda
Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. IEEE Trans. Very Large Scale Integr. Syst. 27 (12) (2019)
Lukás Sekanina, Vojtech Mrazek, Zdenek Vasícek
Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. ICECS (2018)
Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
ADAC: Automated Design of Approximate Circuits. CAV (1) (2018)
Vojtech Mrazek, Zdenek Vasícek, Radek Hrbacek
Role of circuit representation in evolutionary design of energy-efficient approximate circuits. IET Comput. Digit. Tech. 12 (4) (2018)
Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. AHS (2018)
Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Honglan Jiang, Jie Han
Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error. IEEE Trans. Very Large Scale Integr. Syst. 26 (11) (2018)
Vojtech Mrazek, Marek Sýs, Zdenek Vasícek, Lukás Sekanina, Vashek Matyas
Evolving boolean functions for fast and efficient randomness testing. GECCO (2018)
Vojtech Mrazek, Zdenek Vasícek
Evolutionary design of large approximate adders optimized for various error criteria. GECCO (Companion) (2018)
Vojtech Mrazek, Zdenek Vasícek
Parallel optimization of transistor level circuits using cartesian genetic programming. GECCO (Companion) (2017)
Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished. ICCAD (2017)
Zdenek Vasícek, Vojtech Mrazek
Trading between quality and non-functional properties of median filter in embedded systems. Genet. Program. Evolvable Mach. 18 (1) (2017)
Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
Towards low power approximate DCT architecture for HEVC standard. DATE (2017)
Muhammad Shafique, Rehan Hafiz, Muhammad Usama Javed, Sarmad Abbas, Lukás Sekanina, Zdenek Vasícek, Vojtech Mrazek
Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. ISVLSI (2017)
Vojtech Mrazek, Radek Hrbacek, Zdenek Vasícek, Lukás Sekanina
EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. DATE (2017)
Vojtech Mrazek, Zdenek Vasícek
Automatic design of arbitrary-size approximate sorting networks with error guarantee. PATMOS (2016)
Jan Nevoral, Richard Ruzicka, Vojtech Mrazek
Evolutionary design of polymorphic gates using ambipolar transistors. SSCI (2016)
Vojtech Mrazek, Syed Shakib Sarwar, Lukás Sekanina, Zdenek Vasícek, Kaushik Roy
Design of power-efficient approximate multipliers for approximate artificial neural networks. ICCAD (2016)
Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
Evolutionary functional approximation of circuits implemented into FPGAs. SSCI (2016)
Radek Hrbacek, Vojtech Mrazek, Zdenek Vasícek
Automatic design of approximate circuits by means of multi-objective evolutionary algorithms. DTIS (2016)
Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
Evolutionary Approximation of Software for Embedded Systems: Median Function. GECCO (Companion) (2015)
Vojtech Mrazek, Zdenek Vasícek
Evolutionary Design of Transistor Level Digital Circuits Using Discrete Simulation. EuroGP (2015)
Vojtech Mrazek, Zdenek Vasícek
Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers. EUC (2015)
Vojtech Mrazek, Zdenek Vasícek
Acceleration of transistor-level evolution using Xilinx Zynq Platform. ICES (2014)