A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits.
D. A. TranArnaud VirazelAlberto BosioLuigi DililloPatrick GirardSerge PravossoudovitchHans-Joachim WunderlichPublished in: Asian Test Symposium (2011)
Keyphrases
- fault tolerant
- digital circuits
- fault tolerance
- data flow
- evolvable hardware
- functional decomposition
- distributed systems
- model based diagnosis
- state machine
- high availability
- management system
- finite state machines
- database systems
- circuit design
- constraint satisfaction
- interconnection networks
- response time
- decision diagrams
- digital libraries