Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation.
Vladimir HerdtHoang M. LeDaniel GroßeRolf DrechslerPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2019)
Keyphrases
- model checking
- intermediate level
- programming language
- verification method
- formal specification language
- specification language
- simulation models
- language learning
- simulation model
- formal specification
- mathematical model
- databases
- natural language
- real time
- test bed
- signature verification
- artificial intelligence
- asynchronous circuits
- genetic algorithm
- concurrent systems