Saeideh Shirinzadeh

ORCID

Publication Activity (10 Years)

Years Active: 2013-2024
Publications (10 Years): 21

Top Venues

University of Bremen, Germany (PHD)

Education History

University of Bremen, Germany

PHD

Publications

Fatemeh Shirinzadeh, Arighna Deb, Saeideh Shirinzadeh, Abhoy Kole, Kamalika Datta, Rolf Drechsler
In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures. VLSID (2024)
Kamalika Datta, Arighna Deb, Fatemeh Shirinzadeh, Abhoy Kole, Saeideh Shirinzadeh, Rolf Drechsler
Verification of In-Memory Logic Design using ReRAM Crossbars. NEWCAS (2023)
Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler
Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars. ASP-DAC (2023)
Kamalika Datta, Saman Fröhlich, Saeideh Shirinzadeh, Dev Narayan Yadav, Indranil Sengupta, Rolf Drechsler
Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications. VLSI-SoC (2022)
Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler
Parallel Computing of Graph-based Functions in ReRAM. ACM J. Emerg. Technol. Comput. Syst. 18 (2) (2022)
Kamalika Datta, Saeideh Shirinzadeh, Phrangboklang Lyngton Thangkhiew, Indranil Sengupta, Rolf Drechsler
Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles. DSD (2022)
Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler
Multiply-Accumulate Enhanced BDD-Based Logic Synthesis on RRAM Crossbars. ISCAS (2020)
Steffen Frerix, Saeideh Shirinzadeh, Saman Fröhlich, Rolf Drechsler
ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing. NANOARCH (2019)
Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler
Logic Synthesis for Hybrid CMOS-ReRAM Sequential Circuits. ISVLSI (2019)
Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
Logic Synthesis for RRAM-Based In-Memory Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (7) (2018)
Saeideh Shirinzadeh, Kamalika Datta, Rolf Drechsler
Logic Design Using Memristors: An Emerging Technology. ISMVL (2018)
Saeideh Shirinzadeh, Rolf Drechsler
Logic Synthesis for In-memory Computing Using Resistive Memories. ISVLSI (2018)
Mathias Soeken, Pierre-Emmanuel Gaillardon, Saeideh Shirinzadeh, Rolf Drechsler, Giovanni De Micheli
A PLiM Computer for the Internet of Things. Computer 50 (6) (2017)
Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
-preferred evolutionary algorithm for approximate BDD optimization. GECCO (2017)
Arighna Deb, Robert Wille, Oliver Keszöcze, Saeideh Shirinzadeh, Rolf Drechsler
Synthesis of optical circuits using binary decision diagrams. Integr. 59 (2017)
Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler
Endurance management for resistive Logic-In-Memory computing architectures. DATE (2017)
Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs. DATE (2016)
Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm. GECCO (Companion) (2016)
Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler
Multi-objective BDD optimization for RRAM based circuit design. DDECS (2016)
Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli
An MIG-based compiler for programmable logic-in-memory architectures. DAC (2016)
Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler
Multi-Objective BDD Optimization with Evolutionary Algorithms. GECCO (2015)
Rahebeh Niaraki Asli, Saeideh Shirinzadeh
High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design. J. Electron. Test. 29 (4) (2013)

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Publication Activity (10 Years)

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Saeideh Shirinzadeh