Ulrich Kühne

ORCID

Publication Activity (10 Years)

Years Active: 2005-2022
Publications (10 Years): 17

Top Venues

University of Bremen (PHD)

Education History

University of Bremen

PHD

Publications

Maxime Ayrault, Ulrich Kühne, Etienne Borde
Finding Optimal Moving Target Defense Strategies: A Resilience Booster for Connected Cars. Inf. 13 (5) (2022)
Hervé Chabanne, Jean-Luc Danger, Linda Guiga, Ulrich Kühne
Telepathic Headache: Mitigating Cache Side-Channel Attacks on Convolutional Neural Networks. ACNS (1) (2021)
Hervé Chabanne, Jean-Luc Danger, Linda Guiga, Ulrich Kühne
Side channel attacks for architecture extraction of neural networks. CAAI Trans. Intell. Technol. 6 (1) (2021)
Hervé Chabanne, Jean-Luc Danger, Linda Guiga, Ulrich Kühne
Parasite: Mitigating Physical Side-Channel Attacks Against Neural Networks. SPACE (2021)
Lars Tebelmann, Ulrich Kühne, Jean-Luc Danger, Michael Pehl
Analysis and Protection of the Two-Metric Helper Data Scheme. COSADE (2021)
Maxime Ayrault, Etienne Borde, Ulrich Kühne, Jean Leneutre
Moving Target Defense Strategy in Critical Embedded Systems: A Game-theoretic Approach. PRDC (2021)
Lars Tebelmann, Ulrich Kühne, Jean-Luc Danger, Michael Pehl
Analysis and Protection of the Two-metric Helper Data Scheme. IACR Cryptol. ePrint Arch. 2021 (2021)
Jean-Luc Danger, Adrien Facon, Sylvain Guilley, Karine Heydemann, Ulrich Kühne, Abdelmalek Si-Merabet, Michaël Timbert, Baptiste Pecatte
Processor Anchor to Increase the Robustness Against Fault Injection and Cyber Attacks. COSADE (2020)
Jean-Luc Danger, Laurent Fribourg, Ulrich Kühne, Maha Naceur
LAOCOÖN: A Run-Time Monitoring and Verification Approach for Hardware Trojan Detection. DSD (2019)
Maxime Ayrault, Etienne Borde, Ulrich Kühne
Run or Hide? Both! A Method Based on IPv6 Address Switching to Escape While Being Hidden. MTD@CCS (2019)
Jean-Luc Danger, Adrien Facon, Sylvain Guilley, Karine Heydemann, Ulrich Kühne, Abdelmalek Si-Merabet, Michaël Timbert
CCFI-Cache: A Transparent and Flexible Hardware Protection for Code and Control-Flow Integrity. DSD (2018)
Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große, Rolf Drechsler
Behaviour Driven Development for Hardware Design. IPSJ Trans. Syst. LSI Des. Methodol. 11 (2018)
Amr A. R. Sayed-Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
Formal verification of integer multipliers by combining Gröbner basis with logic reduction. DATE (2016)
Amr A. R. Sayed-Ahmed, Ulrich Kühne, Daniel Große, Rolf Drechsler
Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits. ISVLSI (2015)
Laurent Fribourg, Ulrich Kühne, Nicolas Markey
Game-based Synthesis of Distributed Controllers for Sampled Switched Systems. SynCoP (2015)
Arun Chandrasekharan, Kenneth Schmitz, Ulrich Kühne, Rolf Drechsler
Ensuring safety and reliability of IP-based system design - A container approach. RSP (2015)
Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler
A generic representation of CCSL time constraints for UML/MARTE models. DAC (2015)
Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
Automatic refinement checking for formal system models. FDL (2014)
Laurent Fribourg, Ulrich Kühne, Romain Soulat
Finite controlled invariants for sampled switched systems. Formal Methods Syst. Des. 45 (3) (2014)
Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
Behaviour Driven Development for Tests and Verification. TAP@STAF (2014)
Christoph Hilken, Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
Verifying consistency between activity diagrams and their corresponding OCL contracts. FDL (2014)
Rolf Drechsler, Ulrich Kühne
Safe IP Integration Using Container Modules. ISED (2014)
Amr A. R. Sayed-Ahmed, Hossam A. H. Fahmy, Ulrich Kühne
Verification of the decimal floating-point square root operation. ETS (2014)
Laurent Fribourg, Ulrich Kühne, Romain Soulat
Constructing Attractors of Nonlinear Dynamical Systems. FSFMA (2013)
Laurent Fribourg, Ulrich Kühne
Parametric Verification and Test Coverage for Hybrid Automata using the inverse Method. Int. J. Found. Comput. Sci. 24 (2) (2013)
Étienne André, Laurent Fribourg, Ulrich Kühne, Romain Soulat
IMITATOR 2.5: A Tool for Analyzing Robustness in Scheduling Problems. FM (2012)
Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang Minh Le, Julia Seiter, Mathias Soeken, Robert Wille
Completeness-Driven Development. ICGT (2012)
Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
Simulation-based equivalence checking between SystemC models at different levels of abstraction. ACM Great Lakes Symposium on VLSI (2011)
Kim Grüttner, Andreas Herrholz, Ulrich Kühne, Daniel Große, Achim Rettberg, Wolfgang Nebel, Rolf Drechsler
Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines. ISORC Workshops (2011)
Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
Towards Automatic Property Generation for the Formal Verification of Bus Bridges. MBMV (2011)
Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction. MBMV (2011)
Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
Automatic property generation for the formal verification of bus bridges. DDECS (2011)
Laurent Fribourg, Ulrich Kühne
Parametric Verification and Test Coverage for Hybrid Automata Using the Inverse Method. RP (2011)
Ulrich Kühne, Daniel Große, Rolf Drechsler
Towards Fully Automatic Synthesis of Embedded Software. IEEE Embed. Syst. Lett. 2 (3) (2010)
Ulrich Kühne, Sven Beyer, Jörg Bormann, John Barstow
Automated formal verification of processors based on architectural models. FMCAD (2010)
André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler
WoLFram- A Word Level Framework for Formal Verification. IEEE International Workshop on Rapid System Prototyping (2009)
André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
Increasing the Accuracy of SAT-based Debugging. MBMV (2009)
Ulrich Kühne, Daniel Große, Rolf Drechsler
Property analysis and design understanding. DATE (2009)
Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Contradictory antecedent debugging in bounded model checking. ACM Great Lakes Symposium on VLSI (2009)
André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
Increasing the accuracy of SAT-based debugging. DATE (2009)
Ulrich Kühne, Sven Beyer, Christian Pichler
Generating an Efficient Instruction Set Simulator from a Complete Property Suite. IEEE International Workshop on Rapid System Prototyping (2009)
Daniel Große, Ulrich Kühne, Rolf Drechsler
Analyzing Functional Coverage in Bounded Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (7) (2008)
Ulrich Kühne, Daniel Große, Rolf Drechsler
Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow. MTV (2008)
Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking. MBMV (2008)
Daniel Große, Ulrich Kühne, Rolf Drechsler
Estimating functional coverage in bounded model checking. DATE (2007)
Ulrich Kühne, Daniel Große, Rolf Drechsler
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation. ISVLSI (2007)
Ulrich Kühne, Nicole Drechsler
Finding Compact BDDs Using Genetic Programming. EvoWorkshops (2006)
Daniel Große, Ulrich Kühne, Rolf Drechsler
HW/SW co-verification of embedded systems using bounded model checking. ACM Great Lakes Symposium on VLSI (2006)
Daniel Große, Ulrich Kühne, Rolf Drechsler
Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors. GI Jahrestagung (1) (2005)
Daniel Große, Ulrich Kühne, Rolf Drechsler
HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. MTV (2005)

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Publication Activity (10 Years)

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Ulrich Kühne