Nils Przigoda

ORCID

Publication Activity (10 Years)

Years Active: 2012-2023
Publications (10 Years): 18

Top Venues

University of Bremen, Germany (PHD)

Education History

University of Bremen, Germany

PHD

Publications

Domenik Eichhorn, Tobias Pett, Nils Przigoda, Jessica Kindsvater, Christoph Seidl, Ina Schaefer
Coverage-Driven Test Automation for Highly-Configurable Railway Systems. VaMoS (2023)
Stefan Engels, Tom Peham, Judith Przigoda, Nils Przigoda, Robert Wille
Design Tasks and Their Complexity for Hybrid Level 3 of the European Train Control System. CoRR (2023)
Tom Peham, Judith Przigoda, Nils Przigoda, Robert Wille
Optimal Railway Routing Using Virtual Subsections. RSSRail (2022)
Robert Wille, Tom Peham, Judith Przigoda, Nils Przigoda
Towards Automatic Design and Verification for Level 3 of the European Train Control System. DATE (2021)
Nils Przigoda, Judith Przigoda, Robert Wille
Four-Valued Logic in UML/OCL Models: A "Playground" for the MVL Community. ISMVL (2019)
Philipp Niemann, Nils Przigoda, Robert Wille, Rolf Drechsler
Analyzing Frame Conditions in UML/OCL Models - Consistency Equivalence and Independence. MODELSWARD (2018)
Nils Przigoda, Philipp Niemann, Jonas Gomes Filho, Robert Wille, Rolf Drechsler
statements. Comput. Lang. Syst. Struct. 54 (2018)
Philipp Niemann, Nils Przigoda, Robert Wille, Rolf Drechsler
Generation and Validation of Frame Conditions in Formal Models. MODELSWARD (Revised Selected Papers) (2018)
Nils Przigoda, Philipp Niemann, Judith Peters, Frank Hilken, Robert Wille, Rolf Drechsler
More than true or false: native support of irregular values in the automatic validation & verification of UML/OCL models. MEMOCODE (2017)
Pablo González de Aledo, Nils Przigoda, Robert Wille, Rolf Drechsler, Pablo Sánchez Espeso
Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (3) (2017)
Nils Przigoda, Frank Hilken, Judith Peters, Robert Wille, Martin Gogolla, Rolf Drechsler
Integrating an SMT-Based ModelFinder into USE. MoDeVVa@MoDELS (2016)
Jonas Gomes Filho, Nils Przigoda, Robert Wille, Rolf Drechsler
Towards a model-based verification methodology for Complex Swarm Systems (Invited paper). ISED (2016)
Nils Przigoda, Robert Wille, Rolf Drechsler
Analyzing Inconsistencies in UML/OCL Models. J. Circuits Syst. Comput. 25 (3) (2016)
Nils Przigoda, Robert Wille, Rolf Drechsler
Ground setting properties for an efficient translation of OCL in SMT-based model finding. MoDELS (2016)
Nils Przigoda, Gerhard W. Dueck, Robert Wille, Rolf Drechsler
Fault Detection in Parity Preserving Reversible Circuits. ISMVL (2016)
Nils Przigoda, Mathias Soeken, Robert Wille, Rolf Drechsler
Verifying the structure and behavior in UML/OCL models using satisfiability solvers. IET Cyper-Phys. Syst.: Theory & Appl. 1 (1) (2016)
Judith Peters, Nils Przigoda, Robert Wille, Rolf Drechsler
Clocks vs. instants relations: Verifying CCSL time constraints in UML/MARTE models. MEMOCODE (2016)
Nils Przigoda, Jonas Gomes Filho, Philipp Niemann, Robert Wille, Rolf Drechsler
Frame conditions in symbolic representations of UML/OCL models. MEMOCODE (2016)
Nils Przigoda, Judith Peters, Mathias Soeken, Robert Wille, Rolf Drechsler
Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses. MoDeVVa@MoDELS (2015)
Nils Przigoda, Robert Wille, Rolf Drechsler
Leveraging the Analysis for Invariant Independence in Formal System Models. DSD (2015)
Nils Przigoda, Christoph Hilken, Robert Wille, Jan Peleska, Rolf Drechsler
Checking concurrent behavior in UML/OCL models. MoDELS (2015)
Nils Przigoda, Robert Wille, Rolf Drechsler
Verbesserung der Fehlersuche in inkonsistenten formalen Modellen (Erweiterte Zusammenfassung). MBMV (2015)
Nils Przigoda, Robert Wille, Rolf Drechsler
Contradiction Analysis for Inconsistent Formal Models. DDECS (2015)
Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler
A generic representation of CCSL time constraints for UML/MARTE models. DAC (2015)
Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, Rolf Drechsler
Verification-Driven Design Across Abstraction Levels: A Case Study. DSD (2015)
Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits. J. Multiple Valued Log. Soft Comput. 21 (5-6) (2013)
Robert Wille, Nils Przigoda, Rolf Drechsler
A compact and efficient SAT encoding for quantum circuits. AFRICON (2013)
Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines. ISMVL (2012)
Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler
Synthesis of reversible circuits with minimal lines for large functions. ASP-DAC (2012)

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Publication Activity (10 Years)

Top Topics

Top Venues

Nils Przigoda