Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification.
Pablo González de AledoNils PrzigodaRobert WilleRolf DrechslerPablo Sánchez EspesoPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2017)
Keyphrases
- formal specification
- model checking
- abstraction levels
- levels of abstraction
- temporal logic
- formal verification
- verification method
- model checker
- specification language
- object oriented design
- concurrent systems
- specification languages
- formal methods
- process algebra
- data abstraction
- bounded model checking
- formal specification language
- asynchronous circuits
- epistemic logic
- protocol specification
- computation tree logic
- fuzzy logic
- machine learning
- reverse engineering
- databases