André Sülflow

Publication Activity (10 Years)

Years Active: 2006-2015
Publications (10 Years): 0

Top Venues

ATS

Nat. Comput.

Microprocess. Microsystems

IJCCI

University of Bremen, Germany (PHD)

Education History

University of Bremen, Germany

PHD

Publications

Tino Flenker, André Sülflow, Görschwin Fey
Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation. ATS (2015)
Nicole Drechsler, André Sülflow, Rolf Drechsler
Incorporating user preferences in many-objective optimization using relation ε-preferred. Nat. Comput. 14 (3) (2015)
Alexander Finder, André Sülflow, Görschwin Fey
Latency Analysis for Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (4) (2014)
Mehdi Dehbashi, André Sülflow, Görschwin Fey
Automated design debugging in a testbench-based verification environment. Microprocess. Microsystems 37 (2) (2013)
Nicole Drechsler, André Sülflow, Rolf Drechsler
Incorporating User Preferences in Many-Objective Optimization using Relation Epsilon-Preferred. IJCCI (2013)
Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow
FoREnSiC- An Automatic Debugging Environment for C Programs. Haifa Verification Conference (2012)
Alexander Finder, André Sülflow, Görschwin Fey
Latency Analysis for Sequential Circuits. ETS (2011)
Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler
Effective Robustness Analysis Using Bounded Model Checking Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (8) (2011)
Mehdi Dehbashi, André Sülflow, Görschwin Fey
Automated Design Debugging in a Testbench-Based Verification Environment. DSD (2011)
Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
RobuCheck: a robustness checker for digital circuits. DYADEM-FTS@EDCC (2010)
André Sülflow, Rolf Drechsler
Automatic Fault Localization for Programmable Logic Controllers. FORMS/FORMAT (2010)
Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler
Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits). it Inf. Technol. 52 (4) (2010)
André Sülflow, Görschwin Fey, Rolf Drechsler
Using QBF to increase accuracy of SAT-based debugging. ISCAS (2010)
Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
RobuCheck: A Robustness Checker for Digital Circuits. DSD (2010)
André Sülflow
Bounded Fault Tolerance Checking. FDL (2010)
Görschwin Fey, André Sülflow, Rolf Drechsler
Towards Unifying Localization and Explanation for Automated Debugging. MTV (2010)
Robert Wille, Jean Christoph Jung, André Sülflow, Rolf Drechsler
SWORD - Module-based SAT Solving. Algorithms and Applications for Next Generation SAT Solvers (2009)
Görschwin Fey, André Sülflow, Rolf Drechsler
Computing bounds for fault tolerance using formal techniques. DAC (2009)
André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler
WoLFram- A Word Level Framework for Formal Verification. IEEE International Workshop on Rapid System Prototyping (2009)
André Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler
Evaluation of Cardinality Constraints on SMT-Based Debugging. ISMVL (2009)
André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
Increasing the Accuracy of SAT-based Debugging. MBMV (2009)
Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
Robustness Check for Multiple Faults Using Formal Techniques. DSD (2009)
André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
Increasing the accuracy of SAT-based debugging. DATE (2009)
André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Debugging Design Errors by Using Unsatisfiable Cores. MBMV (2008)
André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Using unsatisfiable cores to debug multiple design errors. ACM Great Lakes Symposium on VLSI (2008)
André Sülflow, Görschwin Fey, Rolf Drechsler
Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse. MBMV (2007)
André Sülflow, Rolf Drechsler
Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC. ISMVL (2007)
André Sülflow, Nicole Drechsler, Rolf Drechsler
Robust Multi-Objective Optimization in High Dimensional Spaces. EMO (2006)

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Publication Activity (10 Years)

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André Sülflow