HW/SW Co-Verification of a RISC CPU using Bounded Model Checking.

Daniel Große Ulrich Kühne Rolf Drechsler

Published in: MTV (2005)

Keyphrases

bounded model checking
hw sw
model checking
formal verification
hardware software
design methodology
embedded systems
temporal logic
instruction set
linear temporal logic
multi agent systems
field programmable gate array
hardware and software
formal specification
real time
resource constrained
signal processing