Runtime Monitoring of c-LTL Specifications on FPGAs Using HLS.
Gianluca MartinoGörschwin FeyPublished in: SMACD (2022)
Keyphrases
- bounded model checking
- model checking
- transition systems
- monitoring system
- real time
- linear temporal logic
- model checker
- formal verification
- temporal logic
- concurrent systems
- high level
- formal specification
- functional requirements
- delay insensitive
- condition monitoring
- hardware implementation
- multi agent systems
- control flow
- field programmable gate array
- fpga implementation
- color space
- state space
- neural network