Andreas Steininger

ORCID

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 64

Top Venues

Publications

Alessio Colucci, Andreas Steininger, Muhammad Shafique
SBanTEM: A Novel Methodology for Sparse Band Tensors as Soft-Error Mitigation in Sparse Convolutional Neural Networks. IOLTS (2024)
Clemens Scharwitzl, Andreas Steininger
An Autonomous Clock Frequency Supervision Circuit. DDECS (2024)
Alessio Colucci, Andreas Steininger, Muhammad Shafique
EISFINN: On the Role of Efficient Importance Sampling in Fault Injection Campaigns for Neural Network Robustness Analysis. IOLTS (2024)
Raghda El Shehaby, Matthias Függer, Andreas Steininger
On the Susceptibility of QDI Circuits to Transient Faults. CoRR (2023)
Zaheer Tabassam, Andreas Steininger
SET Effects on Quasi Delay Insensitive and Synchronous Circuits. ETS (2023)
Jürgen Maier, Andreas Steininger, Robert Najvirt
The Hidden Behavior of a D-Latch. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (4) (2023)
Zaheer Tabassam, Andreas Steininger
Towards Resilient Quasi Delay Insensitive Conditional Control Elements. DSD (2023)
Alessio Colucci, Andreas Steininger, Muhammad Shafique
ISimDL: Importance Sampling-Driven Acceleration of Fault Injection Simulations for Evaluating the Robustness of Deep Learning. CoRR (2023)
Zaheer Tabassam, Andreas Steininger, Robert Najvirt, Florian Huemer
ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic. ASYNC (2023)
Mahya Morid Ahmadi, Faiq Khalid, Radha Vaidya, Florian Kriebel, Andreas Steininger, Muhammad Shafique
SHIELD: An Adaptive and Lightweight Defense against the Remote Power Side-Channel Attacks on Multi-tenant FPGAs. CoRR (2023)
Raghda El Shehaby, Matthias Függer, Andreas Steininger
On the Susceptibility of QDI Circuits to Transient Faults. FORMATS (2023)
Alessio Colucci, Andreas Steininger, Muhammad Shafique
enpheeph: A Fault Injection Framework for Spiking and Compressed Deep Neural Networks. CoRR (2022)
Jürgen Maier, Christian Hartl-Nesic, Andreas Steininger
Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (3) (2022)
Zaheer Tabassam, Andreas Steininger
Towards Resilient QDI Pipeline Implementations. DSD (2022)
Florian Huemer, Robert Najvirt, Andreas Steininger
On SAT-Based Model Checking of Speed-Independent Circuits. DDECS (2022)
Zaheer Tabassam, Syed Rameez Naqvi, Andreas Steininger
AµFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline Stages. DDECS (2022)
Raghda El Shehaby, Andreas Steininger
Study and Comparison of QDI Pipeline Components' Sensitivity to Permanent Faults. DFT (2022)
Zaheer Tabassam, Andreas Steininger
SET Hardened Derivatives of QDI Buffer Template. DFT (2022)
Bharath Srinivas Prabakaran, Felix Fasching, Juri Schreib, Andreas Steininger, Muhammad Shafique
ATLAS: An IoT Architecture and Secure Open-source Networking Stack for Anonymous Localization and Tracking Using Smartphones and Bluetooth Beacons. CoRR (2022)
Alessio Colucci, Andreas Steininger, Muhammad Shafique
enpheeph: A Fault Injection Framework for Spiking and Compressed Deep Neural Networks. IROS (2022)
Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger, Zaheer Tabassam
Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. ASYNC (2021)
Raghda El Shehaby, Andreas Steininger
Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines. DDECS (2021)
Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger
An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits. DSD (2021)
Florian Huemer, Andreas Steininger
Timing Domain Crossing using Muller Pipelines. ASYNC (2020)
Andreas Steininger, Robert Najvirt, Jürgen Maier
Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? CoRR (2020)
Andreas Steininger, Jürgen Maier, Robert Najvirt
The Metastable Behavior of a Schmitt-Trigger. CoRR (2020)
Jürgen Maier, Andreas Steininger
Efficient Metastability Characterization for Schmitt-Triggers. CoRR (2020)
Jürgen Maier, Andreas Steininger
Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic. CoRR (2020)
Raghda El Shehaby, Andreas Steininger
On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective. ICCD (2020)
Wolfgang Duer, Andreas Steininger
Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock. DDECS (2020)
Jürgen Maier, Andreas Steininger
Efficient Metastability Characterization for Schmitt-Triggers. ASYNC (2019)
Andrew Paverd, Marcus Völp, Ferdinand Brasser, Matthias Schunter, N. Asokan, Ahmad-Reza Sadeghi, Paulo Jorge Esteves Veríssimo, Andreas Steininger, Thorsten Holz
Sustainable Security & Safety: Challenges and Opportunities. CERTS (2019)
Thomas Polzer, Florian Huemer, Andreas Steininger
An Experimental Study of Metastability-Induced Glitching Behavior. J. Circuits Syst. Comput. 28 (Supplement-1) (2019)
Zoran Stamenkovic, Alberto Bosio, György Cserey, Ondrej Novák, Witold A. Pleskacz, Lukás Sekanina, Andreas Steininger, Goran Stojanovic, Viera Stopjaková
International Symposium on Design and Diagnostics of Electronic Circuits and Systems. ITC (2019)
Florian Huemer, Andreas Steininger
Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication. ASYNC (2018)
Florian Huemer, Thomas Polzer, Andreas Steininger
Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA. DDECS (2018)
Thomas Polzer, Florian Huemer, Andreas Steininger
Refined metastability characterization using a time-to-digital converter. Microelectron. Reliab. 80 (2018)
Markus Schütz, Andreas Steininger, Florian Huemer, Jakob Lechner
State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration. DFT (2018)
Thomas Polzer, Andreas Steininger
A Model for the Metastability Delay of Sequential Elements. J. Circuits Syst. Comput. 26 (8) (2017)
Thomas Polzer, Florian Huemer, Andreas Steininger
Measuring metastability using a time-to-digital converter. DDECS (2017)
Varadan Savulimedu Veeravalli, Andreas Steininger, Ulrich Schmid
A versatile architecture for long-term monitoring of single-event transient durations. Microprocess. Microsystems 53 (2017)
Andreas Steininger, Adam Pawlak, Viera Stopjaková
Foreword. J. Circuits Syst. Comput. 26 (8) (2017)
Bernhard Fritz, Andreas Steininger, Václav Simek, Varadan Savulimedu Veeravalli
Setup for an Experimental Study of Radiation Effects in 65nm CMOS. DSD (2017)
Marko S. Andjelkovic, Milos Krstic, Rolf Kraemer, Varadan Savulimedu Veeravalli, Andreas Steininger
A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study. ATS (2017)
Robert Najvirt, Thomas Polzer, Andreas Steininger
Measuring Metastability with Free-Running Clocks. ASYNC (2017)
Andreas Steininger, Jürgen Maier, Robert Najvirt
The Metastable Behavior of a Schmitt-Trigger. ASYNC (2016)
Thomas Polzer, Robert Najvirt, Florian Beck, Andreas Steininger
On the Appropriate Handling of Metastable Voltages in FPGAs. J. Circuits Syst. Comput. 25 (3) (2016)
Florian Huemer, Jakob Lechner, Andreas Steininger
A new coding scheme for fault tolerant 4-phase delay-insensitive codes. ICCD (2016)
Andreas Steininger, Robert Najvirt, Jürgen Maier
Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? DSD (2016)
Varadan Savulimedu Veeravalli, Andreas Steininger
Study of a delayed single-event effect in the Muller C-element. ETS (2016)
Varadan Savulimedu Veeravalli, Andreas Steininger
Design and Physical Implementation of a Target ASIC for SET Experiments. DSD (2016)
Thomas Polzer, Andreas Steininger
A general approach for comparing metastable behavior of digital CMOS gates. DDECS (2016)
Peter Rössler, Andreas Steininger
Digitale Mikroelektronik in Österreich. Elektrotech. Informationstechnik 132 (6) (2015)
Thomas Polzer, Andreas Steininger
Enhanced Metastability Characterization Based on AC Analysis. DSD (2015)
Thomas Polzer, Andreas Steininger
Measuring the Distribution of Metastable Upsets over Time. DSD (2015)
Andreas Steininger, Horst Zimmermann, Axel Jantsch, Michael Hofbauer, Ulrich Schmid, Kurt Schweiger, Varadan Savulimedu Veeravalli
Building reliable systems-on-chip in nanoscale technologies. Elektrotech. Informationstechnik 132 (6) (2015)
Robert Najvirt, Andreas Steininger
A pausible clock with crystal oscillator accuracy. ECCTD (2015)
Robert Najvirt, Andreas Steininger
How to Synchronize a Pausible Clock to a Reference. ASYNC (2015)
Varadan Savulimedu Veeravalli, Andreas Steininger
Reliable and Continuous Measurement of SET Pulse Widths. DSD (2015)
Jakob Lechner, Andreas Steininger, Florian Huemer
Methods for analysing and improving the fault resilience of delay-insensitive codes. ICCD (2015)
Robert Najvirt, Thomas Polzer, Florian Beck, Andreas Steininger
Containment of Metastable Voltages in FPGAs. DDECS (2015)
Danny Dolev, Matthias Függer, Christoph Lenzen, Ulrich Schmid, Andreas Steininger
Fault-tolerant Distributed Systems in Hardware. Bull. EATCS 116 (2015)
Stefan Resch, Andreas Steininger, Christoph Scherrer
A composable real-time architecture for replicated railway applications. J. Syst. Archit. 61 (9) (2015)
Robert Najvirt, Andreas Steininger
A versatile and reliable glitch filter for clocks. PATMOS (2015)
Thomas Reinbacher, Jörg Brauer, Martin Horauer, Andreas Steininger, Stefan Kowalewski
Runtime verification of microcontroller binary code. Sci. Comput. Program. 80 (2014)
Robert Najvirt, Andreas Steininger
Equivalence of clock gating and synchronization with applicability to GALS communication. PATMOS (2014)
Danny Dolev, Matthias Függer, Markus Posch, Ulrich Schmid, Andreas Steininger, Christoph Lenzen
Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip. J. Comput. Syst. Sci. 80 (4) (2014)
Jürgen Maier, Andreas Steininger
Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic. DDECS (2014)
Varadan Savulimedu Veeravalli, Andreas Steininger
Architecture for monitoring SET propagation in 16-bit Sklansky adder. ISQED (2014)
Syed Rameez Naqvi, Andreas Steininger
A tree arbiter cell for high speed resource sharing in asynchronous environments. DATE (2014)
Syed Rameez Naqvi, Jakob Lechner, Andreas Steininger
Protection of Muller-Pipelines from transient faults. ISQED (2014)
Varadan Savulimedu Veeravalli, Andreas Steininger, Ulrich Schmid
Measuring SET pulsewidths in logic gates using digital infrastructure. ISQED (2014)
Andreas Steininger, Varadan Savulimedu Veeravalli, Dan Alexandrescu, Enrico Costenaro, Lorena Anghel
Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. ICCD (2014)
Robert Najvirt, Syed Rameez Naqvi, Andreas Steininger
Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs. ASYNC (2013)
Thomas Polzer, Andreas Steininger
An Approach for Efficient Metastability Characterization of FPGAs through the Designer. ASYNC (2013)
Thomas Polzer, Andreas Steininger
Digital Late-Transition Metastability Simulation Model. DSD (2013)
Thomas Polzer, Andreas Steininger
Metastability characterization for muller C-elements. PATMOS (2013)
Thomas Polzer, Andreas Steininger
SET propagation in micropipelines. PATMOS (2013)
Varadan Savulimedu Veeravalli, Thomas Polzer, Ulrich Schmid, Andreas Steininger, Michael Hofbauer, Kurt Schweiger, Horst Dietrich, Kerstin Schneider-Hornstein, Horst Zimmermann, Kay-Obbe Voss, Bruno Merk, Michael Hajek
An infrastructure for accurate characterization of single-event transients in digital circuits. Microprocess. Microsystems 37 (8-A) (2013)
Syed Rameez Naqvi, Andreas Steininger, Jakob Lechner
An SET Tolerant Tree Arbiter Cell. ASYNC (2013)
Syed Rameez Naqvi, Robert Najvirt, Andreas Steininger
A Multi-Credit Flow Control scheme for asynchronous NoCs. DDECS (2013)
Stefan Resch, Andreas Steininger, Christoph Scherrer
Software Composability and Mixed Criticality for Triple Modular Redundant Architectures. SASSUR@SAFECOMP (2013)
Danny Dolev, Matthias Függer, Christoph Lenzen, Markus Posch, Ulrich Schmid, Andreas Steininger
FATAL+: A Self-Stabilizing Byzantine Fault-tolerant Clocking Scheme for SoCs CoRR (2012)
Syed Rameez Naqvi, Varadan Savulimedu Veeravalli, Andreas Steininger
Protecting an Asynchronous NoC against Transient Channel Faults. DSD (2012)
Thomas Polzer, Andreas Steininger, Jakob Lechner
Muller C-Element Metastability Containment. PATMOS (2012)
Varadan Savulimedu Veeravalli, Thomas Polzer, Andreas Steininger, Ulrich Schmid
Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. DSD (2012)
Paul Milbredt, Michael Glaß, Martin Lukasiewycz, Andreas Steininger, Jürgen Teich
Designing FlexRay-based automotive architectures: A holistic OEM approach. DATE (2012)
Varadan Savulimedu Veeravalli, Andreas Steininger
Radiation-tolerant combinational gates - an implementation based comparison. DDECS (2012)
Thomas Reinbacher, Jörg Brauer, Daniel Schachinger, Andreas Steininger, Stefan Kowalewski
Automated Test-Trace Inspection for Microcontroller Binary Code. RV (2011)
Gottfried Fuchs, Andreas Steininger
VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation. J. Electr. Comput. Eng. 2011 (2011)
Peter Tummeltshammer, Andreas Steininger
Replicated processors on a single die - How independently do they fail? Elektrotech. Informationstechnik 128 (6) (2011)
Thomas Reinbacher, Jörg Brauer, Martin Horauer, Andreas Steininger, Stefan Kowalewski
Past Time LTL Runtime Verification for Microcontroller Binary Code. FMICS (2011)
Thomas Panhofer, Werner Friesenbichler, Andreas Steininger
Reliability estimation and experimental results of a self-healing asynchronous circuit: A case study. AHS (2010)
Thomas Panhofer, Werner Friesenbichler, Andreas Steininger
Implementation of self-healing asynchronous circuits at the example of a video-processing algorithm. DSN Workshops (2010)
Thomas Reinbacher, Jörg Brauer, Martin Horauer, Andreas Steininger, Stefan Kowalewski
Test-Case Generation for Embedded Binary Code Using Abstract Interpretation. MEMICS (2010)
Marcus Jeitler, Jakob Lechner, Andreas Steininger
Enhancing pipelined processor architectures with fast autonomous recovery of transient faults. DDECS (2010)
Werner Friesenbichler, Thomas Panhofer, Andreas Steininger
A deterministic approach for hardware fault injection in asynchronous QDI logic. DDECS (2010)
Peter Tummeltshammer, Andreas Steininger
On the Risk of Fault Coupling over the Chip Substrate. DSD (2009)
Werner Friesenbichler, Andreas Steininger
Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State Logic. DSD (2009)
Babak Rahbaran, Andreas Steininger
Is Asynchronous Logic More Robust Than Synchronous Logic?. IEEE Trans. Dependable Secur. Comput. 6 (4) (2009)

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Publication Activity (10 Years)

Top Topics

Top Venues

Andreas Steininger