On SAT-Based Model Checking of Speed-Independent Circuits.
Florian HuemerRobert NajvirtAndreas SteiningerPublished in: DDECS (2022)
Keyphrases
- model checking
- bounded model checking
- temporal logic
- formal verification
- computation tree logic
- asynchronous circuits
- planning domains
- temporal properties
- partial order reduction
- symbolic model checking
- finite state
- finite state machines
- model checker
- automated verification
- timed automata
- verification method
- linear temporal logic
- formal specification
- epistemic logic
- reachability analysis
- pspace complete
- concurrent systems
- formal methods
- process algebra
- transition systems
- answer set programming
- satisfiability problem
- multi agent systems
- answer sets
- deterministic finite automaton
- constraint satisfaction problems