Robert Najvirt

Publication Activity (10 Years)

Years Active: 2012-2023
Publications (10 Years): 20

Top Topics

Functional Decomposition

Digital Circuits

Set Valued Attributes

Top Venues

Publications

Jürgen Maier, Andreas Steininger, Robert Najvirt
The Hidden Behavior of a D-Latch. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (4) (2023)
Zaheer Tabassam, Andreas Steininger, Robert Najvirt, Florian Huemer
ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic. ASYNC (2023)
Florian Huemer, Robert Najvirt, Andreas Steininger
On SAT-Based Model Checking of Speed-Independent Circuits. DDECS (2022)
Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger, Zaheer Tabassam
Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. ASYNC (2021)
Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger
An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits. DSD (2021)
Andreas Steininger, Robert Najvirt, Jürgen Maier
Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? CoRR (2020)
Andreas Steininger, Jürgen Maier, Robert Najvirt
The Metastable Behavior of a Schmitt-Trigger. CoRR (2020)
Matthias Függer, Robert Najvirt, Thomas Nowak, Ulrich Schmid
A Faithful Binary Circuit Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Matthias Függer, Jürgen Maier, Robert Najvirt, Thomas Nowak, Ulrich Schmid
A Faithful Binary Circuit Model with Adversarial Noise. CoRR (2020)
Matthias Függer, Jürgen Maier, Robert Najvirt, Thomas Nowak, Ulrich Schmid
A faithful binary circuit model with adversarial noise. DATE (2018)
Robert Najvirt, Thomas Polzer, Andreas Steininger
Measuring Metastability with Free-Running Clocks. ASYNC (2017)
Andreas Steininger, Jürgen Maier, Robert Najvirt
The Metastable Behavior of a Schmitt-Trigger. ASYNC (2016)
Thomas Polzer, Robert Najvirt, Florian Beck, Andreas Steininger
On the Appropriate Handling of Metastable Voltages in FPGAs. J. Circuits Syst. Comput. 25 (3) (2016)
Andreas Steininger, Robert Najvirt, Jürgen Maier
Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? DSD (2016)
Robert Najvirt, Ulrich Schmid, Michael Hofbauer, Matthias Függer, Thomas Nowak, Kurt Schweiger
Experimental Validation of a Faithful Binary Circuit Model. ACM Great Lakes Symposium on VLSI (2015)
Robert Najvirt, Andreas Steininger
A pausible clock with crystal oscillator accuracy. ECCTD (2015)
Robert Najvirt, Andreas Steininger
How to Synchronize a Pausible Clock to a Reference. ASYNC (2015)
Matthias Függer, Robert Najvirt, Thomas Nowak, Ulrich Schmid
Towards binary circuit models that faithfully capture physical solvability. DATE (2015)
Robert Najvirt, Thomas Polzer, Florian Beck, Andreas Steininger
Containment of Metastable Voltages in FPGAs. DDECS (2015)
Robert Najvirt, Andreas Steininger
A versatile and reliable glitch filter for clocks. PATMOS (2015)
Robert Najvirt, Andreas Steininger
Equivalence of clock gating and synchronization with applicability to GALS communication. PATMOS (2014)
Matthias Függer, Robert Najvirt, Thomas Nowak, Ulrich Schmid
Faithful Glitch Propagation in Binary Circuit Models. CoRR (2014)
Robert Najvirt, Syed Rameez Naqvi, Andreas Steininger
Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs. ASYNC (2013)
Syed Rameez Naqvi, Robert Najvirt, Andreas Steininger
A Multi-Credit Flow Control scheme for asynchronous NoCs. DDECS (2013)
Jakob Lechner, Robert Najvirt
A Generic Architecture for Robust Asynchronous Communication Links. PATMOS (2012)