Jakob Lechner

Publication Activity (10 Years)

Years Active: 2009-2020
Publications (10 Years): 6

Top Topics

Formal Verification

Control Program

Bounded Model Checking

Top Venues

ACM Trans. Embed. Comput. Syst.

Publications

Georgy Lukyanov, Andrey Mokhov, Jakob Lechner
Formal Verification of Spacecraft Control Programs. ACM Trans. Embed. Comput. Syst. 19 (5) (2020)
Andrey Mokhov, Georgy Lukyanov, Jakob Lechner
Formal verification of spacecraft control programs (experience report). Haskell@ICFP (2019)
Andrey Mokhov, Georgy Lukyanov, Jakob Lechner
Formal Verification of Spacecraft Control Programs Using a Metalanguage for State Transformers. CoRR (2018)
Markus Schütz, Andreas Steininger, Florian Huemer, Jakob Lechner
State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration. DFT (2018)
Florian Huemer, Jakob Lechner, Andreas Steininger
A new coding scheme for fault tolerant 4-phase delay-insensitive codes. ICCD (2016)
Jakob Lechner, Andreas Steininger, Florian Huemer
Methods for analysing and improving the fault resilience of delay-insensitive codes. ICCD (2015)
Syed Rameez Naqvi, Jakob Lechner, Andreas Steininger
Protection of Muller-Pipelines from transient faults. ISQED (2014)
Syed Rameez Naqvi, Andreas Steininger, Jakob Lechner
An SET Tolerant Tree Arbiter Cell. ASYNC (2013)
Jakob Lechner, Varadan Savulimedu Veeravalli
Modular Redundancy in a GALS System Using Asynchronous Recovery Links. ASYNC (2013)
Jakob Lechner
Designing Robust GALS Circuits with Triple Modular Redundancy. EDCC (2012)
Jakob Lechner, Robert Najvirt
A Generic Architecture for Robust Asynchronous Communication Links. PATMOS (2012)
Jakob Lechner, Martin Lampacher
Protecting pipelined asynchronous communication channels against single event upsets. ICCD (2012)
Thomas Polzer, Andreas Steininger, Jakob Lechner
Muller C-Element Metastability Containment. PATMOS (2012)
Jakob Lechner, Martin Lampacher, Thomas Polzer
A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding. ACSD (2012)
Marcus Jeitler, Jakob Lechner
Low Latency Recovery from Transient Faults for Pipelined Processor Architectures. DSD (2010)
Marcus Jeitler, Jakob Lechner, Andreas Steininger
Enhancing pipelined processor architectures with fast autonomous recovery of transient faults. DDECS (2010)
Marcus Jeitler, Jakob Lechner
Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation. ReConFig (2009)
Marcus Jeitler, Jakob Lechner
Towards Comparing the Robustness of Synchronous and Asynchronous Circuits by Fault Injection. MEMICS (2009)