Varadan Savulimedu Veeravalli

Publication Activity (10 Years)

Years Active: 2012-2017
Publications (10 Years): 7

Top Topics

State Dependent

Supervisory Control

Modular Architecture

Top Venues

Microprocess. Microsystems

Publications

Varadan Savulimedu Veeravalli, Andreas Steininger, Ulrich Schmid
A versatile architecture for long-term monitoring of single-event transient durations. Microprocess. Microsystems 53 (2017)
Bernhard Fritz, Andreas Steininger, Václav Simek, Varadan Savulimedu Veeravalli
Setup for an Experimental Study of Radiation Effects in 65nm CMOS. DSD (2017)
Marko S. Andjelkovic, Milos Krstic, Rolf Kraemer, Varadan Savulimedu Veeravalli, Andreas Steininger
A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study. ATS (2017)
Varadan Savulimedu Veeravalli, Andreas Steininger
Study of a delayed single-event effect in the Muller C-element. ETS (2016)
Varadan Savulimedu Veeravalli, Andreas Steininger
Design and Physical Implementation of a Target ASIC for SET Experiments. DSD (2016)
Andreas Steininger, Horst Zimmermann, Axel Jantsch, Michael Hofbauer, Ulrich Schmid, Kurt Schweiger, Varadan Savulimedu Veeravalli
Building reliable systems-on-chip in nanoscale technologies. Elektrotech. Informationstechnik 132 (6) (2015)
Varadan Savulimedu Veeravalli, Andreas Steininger
Reliable and Continuous Measurement of SET Pulse Widths. DSD (2015)
Varadan Savulimedu Veeravalli, Andreas Steininger
Architecture for monitoring SET propagation in 16-bit Sklansky adder. ISQED (2014)
Varadan Savulimedu Veeravalli, Andreas Steininger, Ulrich Schmid
Measuring SET pulsewidths in logic gates using digital infrastructure. ISQED (2014)
Andreas Steininger, Varadan Savulimedu Veeravalli, Dan Alexandrescu, Enrico Costenaro, Lorena Anghel
Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. ICCD (2014)
Varadan Savulimedu Veeravalli, Thomas Polzer, Ulrich Schmid, Andreas Steininger, Michael Hofbauer, Kurt Schweiger, Horst Dietrich, Kerstin Schneider-Hornstein, Horst Zimmermann, Kay-Obbe Voss, Bruno Merk, Michael Hajek
An infrastructure for accurate characterization of single-event transients in digital circuits. Microprocess. Microsystems 37 (8-A) (2013)
Jakob Lechner, Varadan Savulimedu Veeravalli
Modular Redundancy in a GALS System Using Asynchronous Recovery Links. ASYNC (2013)
Syed Rameez Naqvi, Varadan Savulimedu Veeravalli, Andreas Steininger
Protecting an Asynchronous NoC against Transient Channel Faults. DSD (2012)
Varadan Savulimedu Veeravalli, Thomas Polzer, Andreas Steininger, Ulrich Schmid
Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. DSD (2012)
Varadan Savulimedu Veeravalli, Andreas Steininger
Radiation-tolerant combinational gates - an implementation based comparison. DDECS (2012)