Thomas Polzer

Publication Activity (10 Years)

Years Active: 2009-2023
Publications (10 Years): 13

Top Topics

Set Valued Attributes

Containment Of Conjunctive Queries

Top Venues

J. Circuits Syst. Comput.

Publications

Fabian Steiner, Bernhard Lueger, Bernhard Wallisch, Thomas Polzer
Automated Evaluation System for Microcontroller Assignments. EDUCON (2023)
Thomas Polzer, Florian Huemer, Andreas Steininger
An Experimental Study of Metastability-Induced Glitching Behavior. J. Circuits Syst. Comput. 28 (Supplement-1) (2019)
Florian Huemer, Thomas Polzer, Andreas Steininger
Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA. DDECS (2018)
Thomas Polzer, Florian Huemer, Andreas Steininger
Refined metastability characterization using a time-to-digital converter. Microelectron. Reliab. 80 (2018)
Thomas Polzer, Andreas Steininger
A Model for the Metastability Delay of Sequential Elements. J. Circuits Syst. Comput. 26 (8) (2017)
Thomas Polzer, Florian Huemer, Andreas Steininger
Measuring metastability using a time-to-digital converter. DDECS (2017)
Robert Najvirt, Thomas Polzer, Andreas Steininger
Measuring Metastability with Free-Running Clocks. ASYNC (2017)
Matthias Függer, Attila Kinali, Christoph Lenzen, Thomas Polzer
Metastability-Aware Memory-Efficient Time-to-Digital Converters. ASYNC (2017)
Thomas Polzer, Robert Najvirt, Florian Beck, Andreas Steininger
On the Appropriate Handling of Metastable Voltages in FPGAs. J. Circuits Syst. Comput. 25 (3) (2016)
Thomas Polzer, Andreas Steininger
A general approach for comparing metastable behavior of digital CMOS gates. DDECS (2016)
Thomas Polzer, Andreas Steininger
Enhanced Metastability Characterization Based on AC Analysis. DSD (2015)
Thomas Polzer, Andreas Steininger
Measuring the Distribution of Metastable Upsets over Time. DSD (2015)
Robert Najvirt, Thomas Polzer, Florian Beck, Andreas Steininger
Containment of Metastable Voltages in FPGAs. DDECS (2015)
Thomas Polzer, Andreas Steininger
An Approach for Efficient Metastability Characterization of FPGAs through the Designer. ASYNC (2013)
Thomas Polzer, Andreas Steininger
Digital Late-Transition Metastability Simulation Model. DSD (2013)
Thomas Polzer, Andreas Steininger
Metastability characterization for muller C-elements. PATMOS (2013)
Thomas Polzer, Andreas Steininger
SET propagation in micropipelines. PATMOS (2013)
Varadan Savulimedu Veeravalli, Thomas Polzer, Ulrich Schmid, Andreas Steininger, Michael Hofbauer, Kurt Schweiger, Horst Dietrich, Kerstin Schneider-Hornstein, Horst Zimmermann, Kay-Obbe Voss, Bruno Merk, Michael Hajek
An infrastructure for accurate characterization of single-event transients in digital circuits. Microprocess. Microsystems 37 (8-A) (2013)
Thomas Polzer, Andreas Steininger, Jakob Lechner
Muller C-Element Metastability Containment. PATMOS (2012)
Jakob Lechner, Martin Lampacher, Thomas Polzer
A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding. ACSD (2012)
Varadan Savulimedu Veeravalli, Thomas Polzer, Andreas Steininger, Ulrich Schmid
Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. DSD (2012)
Thomas Polzer, Thomas Handl, Andreas Steininger
A Metastability-Free Multi-synchronous Communication Scheme for SoCs. SSS (2009)