Enhancing pipelined processor architectures with fast autonomous recovery of transient faults.
Marcus JeitlerJakob LechnerAndreas SteiningerPublished in: DDECS (2010)
Keyphrases
- error detection
- error correction
- parallel architecture
- multi core processors
- fault detection
- fault diagnosis
- parallel architectures
- steady state
- single instruction multiple data
- normal operation
- fault isolation
- cooperative
- memory management
- fault tolerance
- parallel processing
- high speed
- test cases
- memory hierarchy
- root cause
- single processor
- fault model
- database systems
- autonomous navigation
- autonomous systems
- robotic systems
- autonomous learning
- failure recovery
- fuzzy logic
- fault detection and isolation