Low Latency Recovery from Transient Faults for Pipelined Processor Architectures.
Marcus JeitlerJakob LechnerPublished in: DSD (2010)
Keyphrases
- low latency
- error detection
- high speed
- high bandwidth
- high throughput
- real time
- highly efficient
- parallel architectures
- virtual machine
- parallel architecture
- massive scale
- stream processing
- parallel processing
- data flow
- instruction set
- data acquisition
- cost effective
- orders of magnitude
- web services
- information systems