On the Risk of Fault Coupling over the Chip Substrate.
Peter TummeltshammerAndreas SteiningerPublished in: DSD (2009)
Keyphrases
- high speed
- fault diagnosis
- fault detection
- analog vlsi
- risk management
- low cost
- decision making
- high density
- risk assessment
- risk factors
- high risk
- physical design
- risk measures
- risk analysis
- single chip
- high bandwidth
- failure modes
- programmable logic
- minimum risk
- expected utility
- vlsi implementation
- evolvable hardware
- fault model
- low power