Jitendra Khare

Publication Activity (10 Years)

Years Active: 1992-2006
Publications (10 Years): 0

Publications

Jitendra Khare, Amit B. Shah, Ashok Raman, Girish Rayas
Embedded Memory Field Returns - Trials and Tribulations. ITC (2006)
Hans T. Heineken, Jitendra Khare
Test Strategies For a 40Gbps Framer SoC. ITC (2004)
Jitendra Khare
Memory Yield Improvement - SoC Design Perspective. ITC (2004)
Jitendra Khare
DFM - A Fabless Perspective. ITC (2003)
John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly
Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. ITC (2001)
John T. Chen, Wojciech Maly, Janusz Rajski, Omar Kebichi, Jitendra Khare
Enabling Embedded Memory Diagnosis via Test Response Compression. VTS (2001)
Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken
Manufacturability and Testability Oriented Synthesis. VLSI Design (2000)
Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, Saghir A. Shaikh, M. d'Abreu
Maximizing Wafer Productivity Through Layout Optimization. VLSI Design (2000)
A. Bommireddy, Jitendra Khare, Saghir A. Shaikh, S.-T. Su
Test and Debug of Networking SoCs: A Case Study. VTS (2000)
Jitendra Khare, Hans T. Heineken, M. d'Abreu
Cost Trade-Offs in System On Chip Designs. VLSI Design (2000)
Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, P. Simon
Design-Manufacturing Interface: Part II - Applications. DATE (1998)
Wojciech Maly, Pranab K. Nag, Hans T. Heineken, Jitendra Khare
Design-Manufacturing Interface: Part I - Vision. DATE (1998)
Hans T. Heineken, Jitendra Khare, Manuel d'Abreu
Manufacturability analysis of standard cell libraries. CICC (1998)
Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz
CAD at the Design-Manufacturing Interface. DAC (1997)
Wojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag
Design for manufacturability in submicron domain. ICCAD (1996)
Jitendra Khare, Wojciech Maly, Nathan Tiday
Fault characterization of standard cell libraries using inductive contamination. VTS (1996)
Jitendra Khare, Wojciech Maly
Inductive Contamination Analysis (ICA) with SRAM Application. ITC (1995)
Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar
Testability-oriented channel routing. VLSI Design (1995)
Dinesh D. Gaitonde, Jitendra Khare, D. M. H. Walker, Wojciech P. Maly
Estimation of reject ratio in testing of combinatorial circuits. VTS (1993)
Derek Feltham, Jitendra Khare, Wojciech Maly
Design for testability view on placement and routing. EURO-DAC (1992)