Retargeting the MIPS-II CPU Core to the RISC-V Architecture.

Sebastian Cieslak Adrian Oleksiak Krzysztof Marcinek Witold A. Pleskacz

Published in: MIXDES (2019)

Keyphrases

instruction set
real time
application specific
hardware architecture
computation intensive
heterogeneous computing
neural network
database systems
high speed
binary images
software architecture
parallel processing
memory hierarchy
level parallelism