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A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies.
Jacek Gradzki
Tomasz Borejko
Witold A. Pleskacz
Published in:
DDECS (2010)
Keyphrases
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low voltage
cmos technology
leakage current
low power
power line
design considerations
power consumption
power management
random access memory
low cost
navigation systems
parallel processing
power dissipation
mixed signal
hardware implementation
response time
nm technology
silicon on insulator