A 5Gb/s equalizer for USB 3.0 receiver in 65 nm CMOS technology.

Jakub Kopanski Witold A. Pleskacz Dariusz Pienkowski

Published in: DDECS (2011)

Keyphrases

cmos technology
decision feedback
low power
high speed
spl times
multipath
low voltage
power consumption
parallel processing
error propagation
smart card
data transmission
mixed signal
power dissipation
computer simulation
low cost
silicon on insulator
image sensor
real time