Peter Malík

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 13

Top Topics

Dedicated Hardware

Mass Spectrometry

Top Venues

Comput. Informatics

Artif. Intell. Rev.

Publications

Jaromír Klarák, Robert Andok, Peter Malík, Ivan Kuric, Mário Ritomský, Ivana Klacková, Hung-Yin Tsai
From Anomaly Detection to Defect Classification. Sensors 24 (2) (2024)
Tomas Rusnak, Tomás Kasanický, Peter Malík, Ján Mojzis, Ján Zelenka, Michal Svicek, Dominik Abrahám, Andrej Halabuk
Crop Mapping without Labels: Investigating Temporal and Spatial Transferability of Crop Classification Models Using a 5-Year Sentinel-2 Series and Machine Learning. Remote. Sens. 15 (13) (2023)
Stefan Kristofík, Matús Kasás, Peter Malík
StarCraft strategy classification of a large human versus human game replay dataset. FedCSIS (2021)
Stefan Kristofík, Matús Kasás, Stefan Neupauer, Peter Malík
StarCraft agent strategic training on a large human versus human game replay dataset. FedCSIS (2020)
Peter Malík, Kristína Knapová, Stefan Kristofík
Instance Segmentation Model Created from Three Semantic Segmentations of Mask, Boundary and Centroid Pixels Verified on GlaS Dataset. FedCSIS (2020)
Ondrej Kachman, Marcel Baláz, Peter Malík
Universal framework for remote firmware updates of low-power devices. Comput. Commun. 139 (2019)
Giang Nguyen, Stefan Dlugolinsky, Martin Bobák, Viet D. Tran, Álvaro López García, Ignacio Heredia, Peter Malík, Ladislav Hluchý
Machine Learning and Deep Learning frameworks and libraries for large-scale data mining: a survey. Artif. Intell. Rev. 52 (1) (2019)
Stefan Kristofík, Peter Malík
Enhancement of fault collection for embedded RAM redundancy analysis considering intersection and orphan faults. Integr. 62 (2018)
Stefan Kristofík, Marcel Baláz, Peter Malík
Hardware redundancy architecture based on reconfigurable logic blocks with persistent high reliability improvement. Microelectron. Reliab. 86 (2018)
Peter Malík
Dedicated Hardware for Complex Mathematical Operations. Comput. Informatics 35 (6) (2016)
Peter Malík
Natural logarithm and division floating-point high throughput co-processor implemented in FPGA. NORCAS (2016)
Peter Malík
High Throughput Floating Point Exponential Function Implemented in FPGA. ISVLSI (2015)
Peter Malík
High Throughput Floating-Point Dividers Implemented in FPGA. DDECS (2015)
Peter Malík
Dedicated hardware architecture for object tracking preprocessing implemented in FPGA. DDECS (2014)
Peter Malík
Highly scalable IP core to accelerate the forward/backward modified discrete cosine transform in MP3 implemented to FPGA and low-power ASIC. IET Circuits Devices Syst. 5 (5) (2011)
Peter Malík, Michal Ufnal, Arkadiusz W. Luczyk, Marcel Baláz, Witold A. Pleskacz
MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio. DDECS (2009)
Peter Malík, Marcel Baláz, Martin Simlastík, Arkadiusz W. Luczyk, Witold A. Pleskacz
Various MDCT implementations in 0.35µm CMOS. DDECS (2008)
Peter Malík, Marcel Baláz, Tomás Pikula, Martin Simlastík
An Improved MDCT IP Core Generator with Architectural Model Simulation. DDECS (2007)
Martin Simlastík, Viera Stopjaková, Libor Majer, Peter Malík
Clockless Implementation of LEON2 for Low-Power Applications. DDECS (2007)
Peter Malík
A Generic IP Core of the Identical Forward and Inverse 12/36-Point MDCT Architecture and an Architectural Model Simulation Toolbox. ICECS (2007)
Martin Simlastík, Peter Malík, Tomás Pikula, Marcel Baláz
FPGA Implementation of a Fast MDCT Algorithm. DDECS (2006)
Peter Malík, Marcel Baláz, Tomás Pikula, Martin Simlastík
MDCT IP Core Generator with Architectural Model Simulation. VLSI-SoC (2006)