Highly scalable IP core to accelerate the forward/backward modified discrete cosine transform in MP3 implemented to FPGA and low-power ASIC.
Peter MalíkPublished in: IET Circuits Devices Syst. (2011)
Keyphrases
- low power
- highly scalable
- single chip
- discrete cosine transform
- forward backward
- high speed
- low cost
- power consumption
- low power consumption
- image compression
- gate array
- digital signal processing
- transform domain
- dct coefficients
- hardware implementation
- jpeg images
- hidden markov models
- power reduction
- filter bank
- blocking artifacts
- hardware architecture
- logic circuits
- dct domain
- compressed images
- coded images
- image coding
- design methodology
- cmos technology
- subband
- signal processing
- feature vectors
- mixed signal
- application specific