Jan Korenek

Publication Activity (10 Years)

Years Active: 2005-2023
Publications (10 Years): 44

Top Topics

Network Traffic

Packet Filtering

Pattern Matching

High Speed Networks

Top Venues

Publications

Michal Kekely, Jan Korenek
Optimizing Packet Classification on FPGA. DDECS (2023)
Jakub Cabal, Vladislav Válek, Martin Spinler, Daniel Kondys, Jan Korenek
400G Ethernet Packet Capture Demo Based on Network Development Kit for FPGAs. INFOCOM Workshops (2023)
Vlastimil Kosar, Lukas Sismis, Jirí Matousek, Jan Korenek
Accelerating IDS Using TLS Pre-Filter in FPGA. ISCC (2023)
Lukas Sismis, Jan Korenek
Analysis of TLS Prefiltering for IDS Acceleration. PAM (2023)
Jirí Matousek, Adam Lucanský, David Janecek, Jozef Sabo, Jan Korenek, Gianni Antichi
ClassBench-ng: Benchmarking Packet Classification Algorithms in the OpenFlow Era. IEEE/ACM Trans. Netw. 30 (5) (2022)
Jakub Cabal, Jiri Sikora, Stepán Friedl, Martin Spinler, Jan Korenek
FPL Demo: 400G FPGA Packet Capture Based on Network Development Kit. FPL (2022)
Roman Vrána, Jan Korenek
Efficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic Analysis. DDECS (2021)
Tomás Fukac, Jirí Matousek, Jan Korenek, Lukás Kekely
Increasing Memory Efficiency of Hash-Based Pattern Matching for High-Speed Networks. FPT (2021)
Tomás Fukac, Jan Korenek, Jirí Matousek
Scalability of Hash-Based Pattern Matching for High-Speed Network Security and Monitoring. ISCC (2021)
Tomás Fukac, Vlastimil Kosar, Jan Korenek, Jirí Matousek
Increasing Throughput of Intrusion Detection Systems by Hash-Based Short String Pre-filter. LCN (2020)
Michal Kekely, Lukás Kekely, Jan Korenek
General memory efficient packet matching FPGA architecture for future high-speed networks. Microprocess. Microsystems 73 (2020)
Lukás Kekely, Jakub Cabal, Viktor Pus, Jan Korenek
Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs. DSD (2020)
Jan Kucera, Diana Andreea Popescu, Han Wang, Andrew W. Moore, Jan Korenek, Gianni Antichi
Enabling Event-Triggered Data Plane Monitoring. SOSR (2020)
Milan Ceska, Vojtech Havlena, Lukás Holík, Jan Korenek, Ondrej Lengál, Denis Matousek, Jirí Matousek, Jakub Semric, Tomás Vojnar
Deep Packet Inspection in FPGAs via Approximate Nondeterministic Automata. CoRR (2019)
Lukás Kekely, Jakub Cabal, Jan Korenek
Effective FPGA Architecture for General CRC. ARCS (2019)
Tomas Fukac, Jan Korenek
Hash-based Pattern Matching for High Speed Networks. DDECS (2019)
Roman Vrana, Jan Korenek, David Novak
Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network Traffic. DDECS (2019)
Milan Ceska, Vojtech Havlena, Lukás Holík, Jan Korenek, Ondrej Lengál, Denis Matousek, Jirí Matousek, Jakub Semric, Tomás Vojnar
Deep Packet Inspection in FPGAs via Approximate Nondeterministic Automata. FCCM (2019)
Jan Kucera, Lukas Kekely, Adam Piecek, Jan Korenek
General IDS Acceleration for High-Speed Networks. ICCD (2018)
Denis Matousek, Jirí Matousek, Jan Korenek
High-Speed Regular Expression Matching with Pipelined Memory-Based Automata. FCCM (2018)
Denis Matousek, Juraj Kubis, Jirí Matousek, Jan Korenek
Regular expression matching with pipelined delayed input DFAs for high-speed networks. ANCS (2018)
Jan Kucera, Diana Andreea Popescu, Gianni Antichi, Jan Korenek, Andrew W. Moore
Seek and Push: Detecting Large Traffic Aggregates in the Dataplane. CoRR (2018)
Lukas Kekely, Martin Spinler, Stepan Friedl, Jiri Sikora, Jan Korenek
Accelerated Wire-Speed Packet Capture at 200 Gbps. FPL (2018)
Lukás Kekely, Martin Spinler, Stepán Friedl, Jiri Sikora, Jan Korenek, Viktor Pus
Demonstration of Full-Duplex Packet Transfers Over PCI Express with Sustained 200 Gbps Throughput. FPT (2018)
Jakub Cabal, Lukás Kekely, Jan Korenek
High-Speed Computation of CRC Codes for FPGAs. FPT (2018)
Lukas Kekely, Martin Spinler, Stepan Friedl, Jiri Sikora, Jan Korenek
Live demonstration of FPGA based networking accelerator for 200 Gbps data transfers. NOMS (2018)
Michal Kekely, Lukas Kekely, Jan Korenek
Memory Aware Packet Matching Architecture for High-Speed Networks. DSD (2018)
Jakub Cabal, Pavel Benácek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek
Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. FPGA (2018)
Michal Kekely, Jan Korenek
Mapping of P4 match action tables to FPGA. FPL (2017)
Pavel Benácek, Viktor Pus, Jan Korenek, Michal Kekely
Line rate programmable packet processing in 100Gb networks. FPL (2017)
Michal Kekely, Jan Korenek
Packet Classification with Limited Memory Resources. DSD (2017)
Roland Dobai, Jan Korenek, Lukás Sekanina
Evolutionary design of hash function pairs for network filters. Appl. Soft Comput. 56 (2017)
Jirí Matousek, Gianni Antichi, Adam Lucansky, Andrew W. Moore, Jan Korenek
ClassBench-ng: Recasting ClassBench after a Decade of Network Evolution. ANCS (2017)
Lukas Kekely, Jan Kucera, Viktor Pus, Jan Korenek, Athanasios V. Vasilakos
Software Defined Monitoring of Application Protocols. IEEE Trans. Computers 65 (2) (2016)
David Grochol, Lukás Sekanina, Martin Zádník, Jan Korenek, Vlastimil Kosar
Evolutionary circuit design for fast FPGA-based classification of network application protocols. Appl. Soft Comput. 38 (2016)
Vlastimil Kosar, Jan Korenek
Dynamically Reconfigurable Architecture with Atomic Configuration Updates for Flexible Regular Expressions Matching in FPGA. DSD (2016)
Roland Dobai, Jan Korenek, Lukás Sekanina
Adaptive development of hash functions in FPGA-based network routers. SSCI (2016)
Denis Matousek, Jan Korenek, Viktor Pus
High-speed regular expression matching with pipelined automata. FPT (2016)
Jan Viktorin, Jan Korenek
Packet processing on FPGA SoC with DPDK. FPL (2016)
Václav Bartos, Jan Korenek
Evaluating Reputation of Internet Entities. AIMS (2016)
Roland Dobai, Jan Korenek
Evolution of Non-Cryptographic Hash Function Pairs for FPGA-Based Network Applications. SSCI (2015)
Viktor Pus, Petr Velan, Lukas Kekely, Jan Korenek, Pavel Minarík
Hardware accelerated flow measurement of 100 Gb ethernet. IM (2015)
David Grochol, Lukás Sekanina, Martin Zádník, Jan Korenek
A Fast FPGA-Based Classification of Application Protocols Optimized Using Cartesian GP. EvoApplications (2015)
Vlastimil Kosar, Jan Korenek
Towards Efficient Field Programmable Pattern Matching Array. DSD (2015)
Lukas Kekely, Viktor Pus, Jan Korenek
Software Defined Monitoring of application protocols. INFOCOM (2014)
Lukas Kekely, Martin Zádník, Jirí Matousek, Jan Korenek
Fast lookup for dynamic packet filtering in FPGA. DDECS (2014)
Milan Dvorak, Jan Korenek
Low latency book handling in FPGA for high frequency trading. DDECS (2014)
Jan Viktorin, Pavol Korcek, Tomas Fukac, Jan Korenek
Network monitoring probe based on Xilinx Zynq. ANCS (2014)
Viktor Pus, Lukas Kekely, Jan Korenek
Design methodology of configurable high performance packet parser for FPGA. DDECS (2014)
Vlastimil Kosar, Jan Korenek
On NFA-split architecture optimizations. DDECS (2014)
Lukas Kekely, Viktor Pus, Pavel Benácek, Jan Korenek
Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring. FPL (2014)
Jan Kastil, Vlastimil Kosar, Jan Korenek
Hardware architecture for the fast pattern matching. DDECS (2013)
Vlastimil Kosar, Martin Zádník, Jan Korenek
NFA reduction for regular expressions matching using FPGA. FPT (2013)
Jan Viktorin, Pavol Korcek, Vlastimil Kosar, Jan Korenek
Framework for fast prototyping of applications running on reconfigurable system on chip. DASIP (2013)
Jan Korenek
Hardware acceleration in computer networks. DDECS (2013)
Jirí Matousek, Martin Skacan, Jan Korenek
Memory efficient IP lookup in 100 GBPS networks. FPL (2013)
Jirí Matousek, Martin Skacan, Jan Korenek
Towards hardware architecture for memory efficient IPv4/IPv6 Lookup in 100 Gbps networks. DDECS (2013)
Viktor Pus, Lukas Kekely, Jan Korenek
Low-latency modular packet header parser for FPGA. ANCS (2012)
Viktor Pus, Jan Korenek
Reducing memory in high-speed packet classification. IWCMC (2012)
Jan Korenek, Pavol Korcek, Vlastimil Kosar, Martin Zádník, Jan Viktorin
A new embedded platform for rapid development of network applications. ANCS (2012)
Viktor Pus, Michal Kajan, Jan Korenek
Hardware architecture for packet classification with prefix coloring. DDECS (2011)
Viktor Pus, Jiri Tobola, Vlastimil Kosar, Jan Kastil, Jan Korenek
Netbench: Framework for Evaluation of Packet Processing Algorithms. ANCS (2011)
Vlastimil Kosar, Jan Korenek
Reduction of FPGA resources for regular expression matching by relation similarity. DDECS (2011)
Jiri Tobola, Jan Korenek
Effective hash-based IPv6 longest prefix match. DDECS (2011)
Jan Korenek, Vlastimil Kosar
NFA split architecture for fast regular expression matching. ANCS (2010)
Jan Kastil, Jan Korenek
Hardware accelerated pattern matching based on Deterministic Finite Automata with perfect hashing. DDECS (2010)
Jan Kastil, Jan Korenek
High speed pattern matching algorithm based on deterministic finite automata with faulty transition table. ANCS (2010)
Michal Kajan, Jan Korenek
Efficient packet classification algorithm based on entropy. ANCS (2010)
Jan Korenek, Vlastimil Kosar
Efficient mapping of nondeterministic automata to FPGA for fast regular expression matching. DDECS (2010)
Viktor Pus, Juraj Blaho, Jan Korenek
Memory optimizations for packet classification algorithms in FPGA. DDECS (2010)
Viktor Pus, Jan Korenek
Fast and scalable packet classification using perfect hash functions. FPGA (2009)
Juraj Blaho, Jan Korenek, Viktor Pus
Memory optimization for packet classification algorithms. ANCS (2009)
Jan Kastil, Jan Korenek, Ondrej Lengál
Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing. DSD (2009)
Petr Kobierský, Jan Korenek, Libor Polcak
Packet header analysis and field extraction for multigigabit networks. DDECS (2009)
Tamas Malek, Tomás Martínek, Jan Korenek
GICS: Generic interconnection system. FPL (2008)
Martin Zádník, Jan Korenek, Petr Kobierský, Ondrej Lengál
Network Probe for Flexible Flow Monitoring. DDECS (2008)
Jan Korenek, Petr Kobierský
Intrusion Detection System Intended for Multigigabit Networks. DDECS (2007)
Jiri Tobola, Zdenek Kotásek, Jan Korenek, Tomás Martínek, Martin Straka
Online Protocol Testing for FPGA Based Fault Tolerant Systems. DSD (2007)
Martin Kosek, Jan Korenek
FlowContext: Flexible Platform for Multigigabit Stateful Packet Processing. FPL (2007)
Tomás Martínek, Jan Korenek, Otto Fucík, Matej Lexa
A Flexible Technique for the Automatic Design of Approximate String Matching Architectures. DDECS (2006)
Martin Zádník, Tomas Pecenka, Jan Korenek
NetFlow Probe Intended for High-Speed Networks. FPL (2005)
Jan Korenek, Lukás Sekanina
Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs. ICES (2005)