Lukas Kekely

Publication Activity (10 Years)

Years Active: 2012-2018
Publications (10 Years): 7

Top Topics

Run Length Coding

Packet Filtering

Hashing Algorithm

Top Venues

Publications

Jan Kucera, Lukas Kekely, Adam Piecek, Jan Korenek
General IDS Acceleration for High-Speed Networks. ICCD (2018)
Lukas Kekely, Martin Spinler, Stepan Friedl, Jiri Sikora, Jan Korenek
Accelerated Wire-Speed Packet Capture at 200 Gbps. FPL (2018)
Lukas Kekely, Martin Spinler, Stepan Friedl, Jiri Sikora, Jan Korenek
Live demonstration of FPGA based networking accelerator for 200 Gbps data transfers. NOMS (2018)
Michal Kekely, Lukas Kekely, Jan Korenek
Memory Aware Packet Matching Architecture for High-Speed Networks. DSD (2018)
Jakub Cabal, Pavel Benácek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek
Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. FPGA (2018)
Lukas Kekely, Jan Kucera, Viktor Pus, Jan Korenek, Athanasios V. Vasilakos
Software Defined Monitoring of Application Protocols. IEEE Trans. Computers 65 (2) (2016)
Viktor Pus, Petr Velan, Lukas Kekely, Jan Korenek, Pavel Minarík
Hardware accelerated flow measurement of 100 Gb ethernet. IM (2015)
Viktor Pus, Lukas Kekely, Tomás Závodník
Using DSP blocks to compute CRC hash in FPGA (abstract only). FPGA (2014)
Lukas Kekely, Viktor Pus, Jan Korenek
Software Defined Monitoring of application protocols. INFOCOM (2014)
Lukas Kekely, Martin Zádník, Jirí Matousek, Jan Korenek
Fast lookup for dynamic packet filtering in FPGA. DDECS (2014)
Tomás Závodník, Lukas Kekely, Viktor Pus
CRC based hashing in FPGA using DSP blocks. DDECS (2014)
Viktor Pus, Lukas Kekely, Jan Korenek
Design methodology of configurable high performance packet parser for FPGA. DDECS (2014)
Lukas Kekely, Viktor Pus, Pavel Benácek, Jan Korenek
Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring. FPL (2014)
Viktor Pus, Lukas Kekely, Jan Korenek
Low-latency modular packet header parser for FPGA. ANCS (2012)